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This driver adds support for the STM CoreSight IP block, allowing any system compoment (HW or SW) to log and aggregate messages via a single entity. The CoreSight STM exposes an application defined number of channels called stimulus port. Configuration is done using entries in sysfs and channels made available to userspace via configfs. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Michael Williams <michael.williams@arm.com> Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
332 lines
16 KiB
Text
332 lines
16 KiB
Text
Coresight - HW Assisted Tracing on ARM
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======================================
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Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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Date: September 11th, 2014
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Introduction
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------------
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Coresight is an umbrella of technologies allowing for the debugging of ARM
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based SoC. It includes solutions for JTAG and HW assisted tracing. This
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document is concerned with the latter.
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HW assisted tracing is becoming increasingly useful when dealing with systems
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that have many SoCs and other components like GPU and DMA engines. ARM has
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developed a HW assisted tracing solution by means of different components, each
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being added to a design at synthesis time to cater to specific tracing needs.
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Components are generally categorised as source, link and sinks and are
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(usually) discovered using the AMBA bus.
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"Sources" generate a compressed stream representing the processor instruction
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path based on tracing scenarios as configured by users. From there the stream
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flows through the coresight system (via ATB bus) using links that are connecting
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the emanating source to a sink(s). Sinks serve as endpoints to the coresight
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implementation, either storing the compressed stream in a memory buffer or
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creating an interface to the outside world where data can be transferred to a
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host without fear of filling up the onboard coresight memory buffer.
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At typical coresight system would look like this:
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*****************************************************************
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**************************** AMBA AXI ****************************===||
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***************************************************************** ||
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^ ^ | ||
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0000000 ::::: 0000000 ::::: ::::: @@@@@@@ ||||||||||||
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0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
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|->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
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| #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
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| # ETM # ::::: | # PTM # ::::: ::::: @ |
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| ##### ^ ^ | ##### ^ ! ^ ! . | |||||||||
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| |->### | ! | |->### | ! | ! . | || DAP ||
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| | # | ! | | # | ! | ! . | |||||||||
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| | . | ! | | . | ! | ! . | | |
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| | . | ! | | . | ! | ! . | | *
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| | . | ! | | . | ! | ! . | | SWD/
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| | . | ! | | . | ! | ! . | | JTAG
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*****************************************************************<-|
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*************************** AMBA Debug APB ************************
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*****************************************************************
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| . ! . ! ! . |
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| . * . * * . |
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*****************************************************************
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******************** Cross Trigger Matrix (CTM) *******************
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*****************************************************************
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| . ^ . . |
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| * ! * * |
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*****************************************************************
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****************** AMBA Advanced Trace Bus (ATB) ******************
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*****************************************************************
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| ! =============== |
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| * ===== F =====<---------|
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| ::::::::: ==== U ====
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|-->:: CTI ::<!! === N ===
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| ::::::::: ! == N ==
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| ^ * == E ==
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| ! &&&&&&&&& IIIIIII == L ==
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|------>&& ETB &&<......II I =======
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| ! &&&&&&&&& II I .
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| ! I I .
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| ! I REP I<..........
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| ! I I
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| !!>&&&&&&&&& II I *Source: ARM ltd.
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|------>& TPIU &<......II I DAP = Debug Access Port
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&&&&&&&&& IIIIIII ETM = Embedded Trace Macrocell
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; PTM = Program Trace Macrocell
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; CTI = Cross Trigger Interface
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* ETB = Embedded Trace Buffer
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To trace port TPIU= Trace Port Interface Unit
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SWD = Serial Wire Debug
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While on target configuration of the components is done via the APB bus,
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all trace data are carried out-of-band on the ATB bus. The CTM provides
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a way to aggregate and distribute signals between CoreSight components.
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The coresight framework provides a central point to represent, configure and
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manage coresight devices on a platform. This first implementation centers on
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the basic tracing functionality, enabling components such ETM/PTM, funnel,
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replicator, TMC, TPIU and ETB. Future work will enable more
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intricate IP blocks such as STM and CTI.
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Acronyms and Classification
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---------------------------
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Acronyms:
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PTM: Program Trace Macrocell
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ETM: Embedded Trace Macrocell
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STM: System trace Macrocell
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ETB: Embedded Trace Buffer
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ITM: Instrumentation Trace Macrocell
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TPIU: Trace Port Interface Unit
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TMC-ETR: Trace Memory Controller, configured as Embedded Trace Router
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TMC-ETF: Trace Memory Controller, configured as Embedded Trace FIFO
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CTI: Cross Trigger Interface
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Classification:
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Source:
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ETMv3.x ETMv4, PTMv1.0, PTMv1.1, STM, STM500, ITM
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Link:
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Funnel, replicator (intelligent or not), TMC-ETR
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Sinks:
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ETBv1.0, ETB1.1, TPIU, TMC-ETF
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Misc:
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CTI
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Device Tree Bindings
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----------------------
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See Documentation/devicetree/bindings/arm/coresight.txt for details.
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As of this writing drivers for ITM, STMs and CTIs are not provided but are
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expected to be added as the solution matures.
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Framework and implementation
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----------------------------
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The coresight framework provides a central point to represent, configure and
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manage coresight devices on a platform. Any coresight compliant device can
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register with the framework for as long as they use the right APIs:
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struct coresight_device *coresight_register(struct coresight_desc *desc);
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void coresight_unregister(struct coresight_device *csdev);
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The registering function is taking a "struct coresight_device *csdev" and
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register the device with the core framework. The unregister function takes
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a reference to a "struct coresight_device", obtained at registration time.
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If everything goes well during the registration process the new devices will
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show up under /sys/bus/coresight/devices, as showns here for a TC2 platform:
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root:~# ls /sys/bus/coresight/devices/
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replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm
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20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm
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root:~#
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The functions take a "struct coresight_device", which looks like this:
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struct coresight_desc {
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enum coresight_dev_type type;
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struct coresight_dev_subtype subtype;
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const struct coresight_ops *ops;
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struct coresight_platform_data *pdata;
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struct device *dev;
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const struct attribute_group **groups;
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};
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The "coresight_dev_type" identifies what the device is, i.e, source link or
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sink while the "coresight_dev_subtype" will characterise that type further.
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The "struct coresight_ops" is mandatory and will tell the framework how to
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perform base operations related to the components, each component having
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a different set of requirement. For that "struct coresight_ops_sink",
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"struct coresight_ops_link" and "struct coresight_ops_source" have been
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provided.
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The next field, "struct coresight_platform_data *pdata" is acquired by calling
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"of_get_coresight_platform_data()", as part of the driver's _probe routine and
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"struct device *dev" gets the device reference embedded in the "amba_device":
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static int etm_probe(struct amba_device *adev, const struct amba_id *id)
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{
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...
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...
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drvdata->dev = &adev->dev;
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...
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}
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Specific class of device (source, link, or sink) have generic operations
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that can be performed on them (see "struct coresight_ops"). The
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"**groups" is a list of sysfs entries pertaining to operations
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specific to that component only. "Implementation defined" customisations are
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expected to be accessed and controlled using those entries.
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Last but not least, "struct module *owner" is expected to be set to reflect
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the information carried in "THIS_MODULE".
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How to use the tracer modules
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-----------------------------
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Before trace collection can start, a coresight sink needs to be identify.
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There is no limit on the amount of sinks (nor sources) that can be enabled at
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any given moment. As a generic operation, all device pertaining to the sink
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class will have an "active" entry in sysfs:
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root:/sys/bus/coresight/devices# ls
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replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm
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20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm
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root:/sys/bus/coresight/devices# ls 20010000.etb
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enable_sink status trigger_cntr
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root:/sys/bus/coresight/devices# echo 1 > 20010000.etb/enable_sink
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root:/sys/bus/coresight/devices# cat 20010000.etb/enable_sink
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1
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root:/sys/bus/coresight/devices#
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At boot time the current etm3x driver will configure the first address
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comparator with "_stext" and "_etext", essentially tracing any instruction
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that falls within that range. As such "enabling" a source will immediately
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trigger a trace capture:
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root:/sys/bus/coresight/devices# echo 1 > 2201c000.ptm/enable_source
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root:/sys/bus/coresight/devices# cat 2201c000.ptm/enable_source
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1
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root:/sys/bus/coresight/devices# cat 20010000.etb/status
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Depth: 0x2000
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Status: 0x1
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RAM read ptr: 0x0
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RAM wrt ptr: 0x19d3 <----- The write pointer is moving
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Trigger cnt: 0x0
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Control: 0x1
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Flush status: 0x0
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Flush ctrl: 0x2001
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root:/sys/bus/coresight/devices#
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Trace collection is stopped the same way:
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root:/sys/bus/coresight/devices# echo 0 > 2201c000.ptm/enable_source
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root:/sys/bus/coresight/devices#
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The content of the ETB buffer can be harvested directly from /dev:
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root:/sys/bus/coresight/devices# dd if=/dev/20010000.etb \
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of=~/cstrace.bin
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64+0 records in
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64+0 records out
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32768 bytes (33 kB) copied, 0.00125258 s, 26.2 MB/s
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root:/sys/bus/coresight/devices#
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The file cstrace.bin can be decompressed using "ptm2human", DS-5 or Trace32.
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Following is a DS-5 output of an experimental loop that increments a variable up
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to a certain value. The example is simple and yet provides a glimpse of the
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wealth of possibilities that coresight provides.
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Info Tracing enabled
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Instruction 106378866 0x8026B53C E52DE004 false PUSH {lr}
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Instruction 0 0x8026B540 E24DD00C false SUB sp,sp,#0xc
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Instruction 0 0x8026B544 E3A03000 false MOV r3,#0
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Instruction 0 0x8026B548 E58D3004 false STR r3,[sp,#4]
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Instruction 0 0x8026B54C E59D3004 false LDR r3,[sp,#4]
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Instruction 0 0x8026B550 E3530004 false CMP r3,#4
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Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
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Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
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Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
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Timestamp Timestamp: 17106715833
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Instruction 319 0x8026B54C E59D3004 false LDR r3,[sp,#4]
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Instruction 0 0x8026B550 E3530004 false CMP r3,#4
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Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
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Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
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Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
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Instruction 9 0x8026B54C E59D3004 false LDR r3,[sp,#4]
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Instruction 0 0x8026B550 E3530004 false CMP r3,#4
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Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
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Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
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Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
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Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4]
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Instruction 0 0x8026B550 E3530004 false CMP r3,#4
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Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
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Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
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Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
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Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4]
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Instruction 0 0x8026B550 E3530004 false CMP r3,#4
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Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
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Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
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Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
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Instruction 10 0x8026B54C E59D3004 false LDR r3,[sp,#4]
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Instruction 0 0x8026B550 E3530004 false CMP r3,#4
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Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
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Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
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Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
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Instruction 6 0x8026B560 EE1D3F30 false MRC p15,#0x0,r3,c13,c0,#1
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Instruction 0 0x8026B564 E1A0100D false MOV r1,sp
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Instruction 0 0x8026B568 E3C12D7F false BIC r2,r1,#0x1fc0
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Instruction 0 0x8026B56C E3C2203F false BIC r2,r2,#0x3f
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Instruction 0 0x8026B570 E59D1004 false LDR r1,[sp,#4]
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Instruction 0 0x8026B574 E59F0010 false LDR r0,[pc,#16] ; [0x8026B58C] = 0x80550368
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Instruction 0 0x8026B578 E592200C false LDR r2,[r2,#0xc]
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Instruction 0 0x8026B57C E59221D0 false LDR r2,[r2,#0x1d0]
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Instruction 0 0x8026B580 EB07A4CF true BL {pc}+0x1e9344 ; 0x804548c4
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Info Tracing enabled
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Instruction 13570831 0x8026B584 E28DD00C false ADD sp,sp,#0xc
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Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc}
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Timestamp Timestamp: 17107041535
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How to use the STM module
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-------------------------
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Using the System Trace Macrocell module is the same as the tracers - the only
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difference is that clients are driving the trace capture rather
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than the program flow through the code.
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As with any other CoreSight component, specifics about the STM tracer can be
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found in sysfs with more information on each entry being found in [1]:
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root@genericarmv8:~# ls /sys/bus/coresight/devices/20100000.stm
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enable_source hwevent_select port_enable subsystem uevent
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hwevent_enable mgmt port_select traceid
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root@genericarmv8:~#
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Like any other source a sink needs to be identified and the STM enabled before
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being used:
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root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/20010000.etf/enable_sink
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root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/20100000.stm/enable_source
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From there user space applications can request and use channels using the devfs
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interface provided for that purpose by the generic STM API:
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root@genericarmv8:~# ls -l /dev/20100000.stm
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crw------- 1 root root 10, 61 Jan 3 18:11 /dev/20100000.stm
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root@genericarmv8:~#
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Details on how to use the generic STM API can be found here [2].
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[1]. Documentation/ABI/testing/sysfs-bus-coresight-devices-stm
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[2]. Documentation/trace/stm.txt
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