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![Christian König](/assets/img/avatar_default.png)
Instead of per device track the VRAM lost per context and return ECANCELED instead of ENODEV. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
415 lines
9.7 KiB
C
415 lines
9.7 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: monk liu <monk.liu@amd.com>
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*/
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#include <drm/drmP.h>
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#include <drm/drm_auth.h>
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#include "amdgpu.h"
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#include "amdgpu_sched.h"
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static int amdgpu_ctx_priority_permit(struct drm_file *filp,
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enum amd_sched_priority priority)
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{
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/* NORMAL and below are accessible by everyone */
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if (priority <= AMD_SCHED_PRIORITY_NORMAL)
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return 0;
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if (capable(CAP_SYS_NICE))
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return 0;
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if (drm_is_current_master(filp))
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return 0;
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return -EACCES;
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}
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static int amdgpu_ctx_init(struct amdgpu_device *adev,
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enum amd_sched_priority priority,
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struct drm_file *filp,
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struct amdgpu_ctx *ctx)
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{
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unsigned i, j;
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int r;
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if (priority < 0 || priority >= AMD_SCHED_PRIORITY_MAX)
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return -EINVAL;
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r = amdgpu_ctx_priority_permit(filp, priority);
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if (r)
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return r;
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memset(ctx, 0, sizeof(*ctx));
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ctx->adev = adev;
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kref_init(&ctx->refcount);
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spin_lock_init(&ctx->ring_lock);
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ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS,
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sizeof(struct dma_fence*), GFP_KERNEL);
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if (!ctx->fences)
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return -ENOMEM;
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mutex_init(&ctx->lock);
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
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ctx->rings[i].sequence = 1;
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ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i];
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}
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ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);
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ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
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ctx->init_priority = priority;
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ctx->override_priority = AMD_SCHED_PRIORITY_UNSET;
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/* create context entity for each ring */
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for (i = 0; i < adev->num_rings; i++) {
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struct amdgpu_ring *ring = adev->rings[i];
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struct amd_sched_rq *rq;
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rq = &ring->sched.sched_rq[priority];
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if (ring == &adev->gfx.kiq.ring)
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continue;
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r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
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rq, amdgpu_sched_jobs);
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if (r)
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goto failed;
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}
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r = amdgpu_queue_mgr_init(adev, &ctx->queue_mgr);
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if (r)
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goto failed;
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return 0;
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failed:
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for (j = 0; j < i; j++)
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amd_sched_entity_fini(&adev->rings[j]->sched,
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&ctx->rings[j].entity);
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kfree(ctx->fences);
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ctx->fences = NULL;
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return r;
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}
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static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
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{
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struct amdgpu_device *adev = ctx->adev;
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unsigned i, j;
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if (!adev)
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return;
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
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for (j = 0; j < amdgpu_sched_jobs; ++j)
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dma_fence_put(ctx->rings[i].fences[j]);
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kfree(ctx->fences);
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ctx->fences = NULL;
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for (i = 0; i < adev->num_rings; i++)
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amd_sched_entity_fini(&adev->rings[i]->sched,
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&ctx->rings[i].entity);
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amdgpu_queue_mgr_fini(adev, &ctx->queue_mgr);
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mutex_destroy(&ctx->lock);
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}
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static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
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struct amdgpu_fpriv *fpriv,
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struct drm_file *filp,
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enum amd_sched_priority priority,
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uint32_t *id)
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{
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struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
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struct amdgpu_ctx *ctx;
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int r;
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ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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mutex_lock(&mgr->lock);
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r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
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if (r < 0) {
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mutex_unlock(&mgr->lock);
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kfree(ctx);
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return r;
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}
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*id = (uint32_t)r;
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r = amdgpu_ctx_init(adev, priority, filp, ctx);
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if (r) {
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idr_remove(&mgr->ctx_handles, *id);
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*id = 0;
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kfree(ctx);
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}
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mutex_unlock(&mgr->lock);
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return r;
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}
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static void amdgpu_ctx_do_release(struct kref *ref)
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{
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struct amdgpu_ctx *ctx;
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ctx = container_of(ref, struct amdgpu_ctx, refcount);
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amdgpu_ctx_fini(ctx);
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kfree(ctx);
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}
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static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
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{
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struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
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struct amdgpu_ctx *ctx;
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mutex_lock(&mgr->lock);
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ctx = idr_remove(&mgr->ctx_handles, id);
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if (ctx)
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kref_put(&ctx->refcount, amdgpu_ctx_do_release);
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mutex_unlock(&mgr->lock);
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return ctx ? 0 : -EINVAL;
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}
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static int amdgpu_ctx_query(struct amdgpu_device *adev,
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struct amdgpu_fpriv *fpriv, uint32_t id,
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union drm_amdgpu_ctx_out *out)
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{
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struct amdgpu_ctx *ctx;
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struct amdgpu_ctx_mgr *mgr;
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unsigned reset_counter;
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if (!fpriv)
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return -EINVAL;
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mgr = &fpriv->ctx_mgr;
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mutex_lock(&mgr->lock);
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ctx = idr_find(&mgr->ctx_handles, id);
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if (!ctx) {
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mutex_unlock(&mgr->lock);
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return -EINVAL;
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}
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/* TODO: these two are always zero */
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out->state.flags = 0x0;
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out->state.hangs = 0x0;
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/* determine if a GPU reset has occured since the last call */
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reset_counter = atomic_read(&adev->gpu_reset_counter);
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/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
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if (ctx->reset_counter == reset_counter)
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out->state.reset_status = AMDGPU_CTX_NO_RESET;
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else
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out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
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ctx->reset_counter = reset_counter;
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mutex_unlock(&mgr->lock);
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return 0;
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}
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int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp)
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{
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int r;
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uint32_t id;
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enum amd_sched_priority priority;
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union drm_amdgpu_ctx *args = data;
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struct amdgpu_device *adev = dev->dev_private;
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struct amdgpu_fpriv *fpriv = filp->driver_priv;
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r = 0;
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id = args->in.ctx_id;
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priority = amdgpu_to_sched_priority(args->in.priority);
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/* For backwards compatibility reasons, we need to accept
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* ioctls with garbage in the priority field */
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if (priority == AMD_SCHED_PRIORITY_INVALID)
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priority = AMD_SCHED_PRIORITY_NORMAL;
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switch (args->in.op) {
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case AMDGPU_CTX_OP_ALLOC_CTX:
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r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id);
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args->out.alloc.ctx_id = id;
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break;
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case AMDGPU_CTX_OP_FREE_CTX:
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r = amdgpu_ctx_free(fpriv, id);
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break;
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case AMDGPU_CTX_OP_QUERY_STATE:
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r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
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break;
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default:
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return -EINVAL;
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}
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return r;
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}
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struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)
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{
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struct amdgpu_ctx *ctx;
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struct amdgpu_ctx_mgr *mgr;
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if (!fpriv)
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return NULL;
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mgr = &fpriv->ctx_mgr;
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mutex_lock(&mgr->lock);
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ctx = idr_find(&mgr->ctx_handles, id);
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if (ctx)
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kref_get(&ctx->refcount);
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mutex_unlock(&mgr->lock);
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return ctx;
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}
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int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
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{
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if (ctx == NULL)
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return -EINVAL;
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kref_put(&ctx->refcount, amdgpu_ctx_do_release);
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return 0;
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}
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int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
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struct dma_fence *fence, uint64_t* handler)
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{
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struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
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uint64_t seq = cring->sequence;
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unsigned idx = 0;
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struct dma_fence *other = NULL;
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idx = seq & (amdgpu_sched_jobs - 1);
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other = cring->fences[idx];
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if (other)
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BUG_ON(!dma_fence_is_signaled(other));
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dma_fence_get(fence);
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spin_lock(&ctx->ring_lock);
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cring->fences[idx] = fence;
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cring->sequence++;
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spin_unlock(&ctx->ring_lock);
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dma_fence_put(other);
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if (handler)
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*handler = seq;
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return 0;
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}
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struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
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struct amdgpu_ring *ring, uint64_t seq)
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{
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struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
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struct dma_fence *fence;
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spin_lock(&ctx->ring_lock);
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if (seq == ~0ull)
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seq = ctx->rings[ring->idx].sequence - 1;
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if (seq >= cring->sequence) {
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spin_unlock(&ctx->ring_lock);
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return ERR_PTR(-EINVAL);
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}
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if (seq + amdgpu_sched_jobs < cring->sequence) {
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spin_unlock(&ctx->ring_lock);
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return NULL;
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}
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fence = dma_fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]);
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spin_unlock(&ctx->ring_lock);
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return fence;
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}
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void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
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enum amd_sched_priority priority)
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{
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int i;
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struct amdgpu_device *adev = ctx->adev;
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struct amd_sched_rq *rq;
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struct amd_sched_entity *entity;
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struct amdgpu_ring *ring;
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enum amd_sched_priority ctx_prio;
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ctx->override_priority = priority;
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ctx_prio = (ctx->override_priority == AMD_SCHED_PRIORITY_UNSET) ?
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ctx->init_priority : ctx->override_priority;
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for (i = 0; i < adev->num_rings; i++) {
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ring = adev->rings[i];
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entity = &ctx->rings[i].entity;
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rq = &ring->sched.sched_rq[ctx_prio];
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if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
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continue;
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amd_sched_entity_set_rq(entity, rq);
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}
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}
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int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id)
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{
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struct amdgpu_ctx_ring *cring = &ctx->rings[ring_id];
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unsigned idx = cring->sequence & (amdgpu_sched_jobs - 1);
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struct dma_fence *other = cring->fences[idx];
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if (other) {
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signed long r;
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r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
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if (r < 0) {
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DRM_ERROR("Error (%ld) waiting for fence!\n", r);
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return r;
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}
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}
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return 0;
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}
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void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
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{
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mutex_init(&mgr->lock);
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idr_init(&mgr->ctx_handles);
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}
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void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
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{
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struct amdgpu_ctx *ctx;
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struct idr *idp;
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uint32_t id;
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idp = &mgr->ctx_handles;
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idr_for_each_entry(idp, ctx, id) {
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if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
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DRM_ERROR("ctx %p is still alive\n", ctx);
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}
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idr_destroy(&mgr->ctx_handles);
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mutex_destroy(&mgr->lock);
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}
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