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![Horace Chen](/assets/img/avatar_default.png)
SR-IOV need to exchange some data between PF&VF through shared VRAM PF will copy some necessary firmware and information to the shared VRAM. It also requires some information from VF. PF will send a key through mailbox2 to help guest calculate checksum so that it can verify whether the data is correct. So check the data on the specified offset of the shared VRAM, if the checksum is right, read values from it and write some VF information next to the data from PF. Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
351 lines
9.4 KiB
C
351 lines
9.4 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#define MAX_KIQ_REG_WAIT 100000
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int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
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{
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int r;
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void *ptr;
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r = amdgpu_bo_create_kernel(adev, AMDGPU_CSA_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM, &adev->virt.csa_obj,
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&adev->virt.csa_vmid0_addr, &ptr);
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if (r)
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return r;
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memset(ptr, 0, AMDGPU_CSA_SIZE);
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return 0;
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}
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/*
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* amdgpu_map_static_csa should be called during amdgpu_vm_init
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* it maps virtual address "AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE"
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* to this VM, and each command submission of GFX should use this virtual
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* address within META_DATA init package to support SRIOV gfx preemption.
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*/
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int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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struct amdgpu_bo_va **bo_va)
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{
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struct ww_acquire_ctx ticket;
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struct list_head list;
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struct amdgpu_bo_list_entry pd;
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struct ttm_validate_buffer csa_tv;
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int r;
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INIT_LIST_HEAD(&list);
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INIT_LIST_HEAD(&csa_tv.head);
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csa_tv.bo = &adev->virt.csa_obj->tbo;
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csa_tv.shared = true;
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list_add(&csa_tv.head, &list);
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amdgpu_vm_get_pd_bo(vm, &list, &pd);
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r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
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if (r) {
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DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r);
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return r;
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}
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*bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj);
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if (!*bo_va) {
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ttm_eu_backoff_reservation(&ticket, &list);
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DRM_ERROR("failed to create bo_va for static CSA\n");
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return -ENOMEM;
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}
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r = amdgpu_vm_alloc_pts(adev, (*bo_va)->base.vm, AMDGPU_CSA_VADDR,
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AMDGPU_CSA_SIZE);
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if (r) {
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DRM_ERROR("failed to allocate pts for static CSA, err=%d\n", r);
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amdgpu_vm_bo_rmv(adev, *bo_va);
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ttm_eu_backoff_reservation(&ticket, &list);
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return r;
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}
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r = amdgpu_vm_bo_map(adev, *bo_va, AMDGPU_CSA_VADDR, 0, AMDGPU_CSA_SIZE,
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AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |
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AMDGPU_PTE_EXECUTABLE);
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if (r) {
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DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);
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amdgpu_vm_bo_rmv(adev, *bo_va);
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ttm_eu_backoff_reservation(&ticket, &list);
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return r;
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}
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ttm_eu_backoff_reservation(&ticket, &list);
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return 0;
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}
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void amdgpu_virt_init_setting(struct amdgpu_device *adev)
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{
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/* enable virtual display */
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adev->mode_info.num_crtc = 1;
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adev->enable_virtual_display = true;
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adev->cg_flags = 0;
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adev->pg_flags = 0;
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mutex_init(&adev->virt.lock_reset);
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}
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uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
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{
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signed long r;
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uint32_t val;
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struct dma_fence *f;
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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struct amdgpu_ring *ring = &kiq->ring;
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BUG_ON(!ring->funcs->emit_rreg);
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mutex_lock(&kiq->ring_mutex);
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amdgpu_ring_alloc(ring, 32);
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amdgpu_ring_emit_rreg(ring, reg);
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amdgpu_fence_emit(ring, &f);
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amdgpu_ring_commit(ring);
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mutex_unlock(&kiq->ring_mutex);
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r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT));
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dma_fence_put(f);
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if (r < 1) {
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DRM_ERROR("wait for kiq fence error: %ld.\n", r);
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return ~0;
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}
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val = adev->wb.wb[adev->virt.reg_val_offs];
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return val;
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}
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void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
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{
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signed long r;
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struct dma_fence *f;
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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struct amdgpu_ring *ring = &kiq->ring;
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BUG_ON(!ring->funcs->emit_wreg);
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mutex_lock(&kiq->ring_mutex);
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amdgpu_ring_alloc(ring, 32);
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amdgpu_ring_emit_wreg(ring, reg, v);
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amdgpu_fence_emit(ring, &f);
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amdgpu_ring_commit(ring);
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mutex_unlock(&kiq->ring_mutex);
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r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT));
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if (r < 1)
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DRM_ERROR("wait for kiq fence error: %ld.\n", r);
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dma_fence_put(f);
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}
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/**
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* amdgpu_virt_request_full_gpu() - request full gpu access
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* @amdgpu: amdgpu device.
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* @init: is driver init time.
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* When start to init/fini driver, first need to request full gpu access.
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* Return: Zero if request success, otherwise will return error.
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*/
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int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->req_full_gpu) {
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r = virt->ops->req_full_gpu(adev, init);
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if (r)
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return r;
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adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_release_full_gpu() - release full gpu access
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* @amdgpu: amdgpu device.
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* @init: is driver init time.
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* When finishing driver init/fini, need to release full gpu access.
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* Return: Zero if release success, otherwise will returen error.
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*/
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int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->rel_full_gpu) {
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r = virt->ops->rel_full_gpu(adev, init);
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if (r)
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return r;
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_reset_gpu() - reset gpu
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* @amdgpu: amdgpu device.
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* Send reset command to GPU hypervisor to reset GPU that VM is using
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* Return: Zero if reset success, otherwise will return error.
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*/
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int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->reset_gpu) {
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r = virt->ops->reset_gpu(adev);
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if (r)
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return r;
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adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_alloc_mm_table() - alloc memory for mm table
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* @amdgpu: amdgpu device.
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* MM table is used by UVD and VCE for its initialization
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* Return: Zero if allocate success.
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*/
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int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
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{
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int r;
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if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
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return 0;
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r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->virt.mm_table.bo,
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&adev->virt.mm_table.gpu_addr,
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(void *)&adev->virt.mm_table.cpu_addr);
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if (r) {
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DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
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return r;
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}
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memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
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DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
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adev->virt.mm_table.gpu_addr,
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adev->virt.mm_table.cpu_addr);
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return 0;
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}
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/**
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* amdgpu_virt_free_mm_table() - free mm table memory
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* @amdgpu: amdgpu device.
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* Free MM table memory
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*/
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void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
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{
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if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
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return;
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amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
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&adev->virt.mm_table.gpu_addr,
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(void *)&adev->virt.mm_table.cpu_addr);
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adev->virt.mm_table.gpu_addr = 0;
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}
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int amdgpu_virt_fw_reserve_get_checksum(void *obj,
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unsigned long obj_size,
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unsigned int key,
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unsigned int chksum)
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{
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unsigned int ret = key;
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unsigned long i = 0;
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unsigned char *pos;
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pos = (char *)obj;
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/* calculate checksum */
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for (i = 0; i < obj_size; ++i)
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ret += *(pos + i);
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/* minus the chksum itself */
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pos = (char *)&chksum;
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for (i = 0; i < sizeof(chksum); ++i)
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ret -= *(pos + i);
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return ret;
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}
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void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
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{
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uint32_t pf2vf_ver = 0;
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uint32_t pf2vf_size = 0;
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uint32_t checksum = 0;
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uint32_t checkval;
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char *str;
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adev->virt.fw_reserve.p_pf2vf = NULL;
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adev->virt.fw_reserve.p_vf2pf = NULL;
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if (adev->fw_vram_usage.va != NULL) {
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adev->virt.fw_reserve.p_pf2vf =
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(struct amdgim_pf2vf_info_header *)(
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adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
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pf2vf_ver = adev->virt.fw_reserve.p_pf2vf->version;
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AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
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AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
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/* pf2vf message must be in 4K */
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if (pf2vf_size > 0 && pf2vf_size < 4096) {
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checkval = amdgpu_virt_fw_reserve_get_checksum(
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adev->virt.fw_reserve.p_pf2vf, pf2vf_size,
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adev->virt.fw_reserve.checksum_key, checksum);
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if (checkval == checksum) {
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adev->virt.fw_reserve.p_vf2pf =
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((void *)adev->virt.fw_reserve.p_pf2vf +
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pf2vf_size);
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memset((void *)adev->virt.fw_reserve.p_vf2pf, 0,
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sizeof(amdgim_vf2pf_info));
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AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.version,
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AMDGPU_FW_VRAM_VF2PF_VER);
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AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.size,
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sizeof(amdgim_vf2pf_info));
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AMDGPU_FW_VRAM_VF2PF_READ(adev, driver_version,
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&str);
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if (THIS_MODULE->version != NULL)
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strcpy(str, THIS_MODULE->version);
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else
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strcpy(str, "N/A");
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AMDGPU_FW_VRAM_VF2PF_WRITE(adev, driver_cert,
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0);
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AMDGPU_FW_VRAM_VF2PF_WRITE(adev, checksum,
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amdgpu_virt_fw_reserve_get_checksum(
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adev->virt.fw_reserve.p_vf2pf,
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pf2vf_size,
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adev->virt.fw_reserve.checksum_key, 0));
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}
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}
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}
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}
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