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![Horace Chen](/assets/img/avatar_default.png)
SR-IOV need to exchange some data between PF&VF through shared VRAM PF will copy some necessary firmware and information to the shared VRAM. It also requires some information from VF. PF will send a key through mailbox2 to help guest calculate checksum so that it can verify whether the data is correct. So check the data on the specified offset of the shared VRAM, if the checksum is right, read values from it and write some VF information next to the data from PF. Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
357 lines
9.7 KiB
C
357 lines
9.7 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "vega10/soc15ip.h"
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#include "vega10/NBIO/nbio_6_1_offset.h"
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#include "vega10/NBIO/nbio_6_1_sh_mask.h"
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#include "vega10/GC/gc_9_0_offset.h"
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#include "vega10/GC/gc_9_0_sh_mask.h"
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#include "soc15.h"
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#include "vega10_ih.h"
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#include "soc15_common.h"
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#include "mxgpu_ai.h"
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static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev)
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{
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u32 reg;
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int timeout = AI_MAILBOX_TIMEDOUT;
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u32 mask = REG_FIELD_MASK(BIF_BX_PF0_MAILBOX_CONTROL, RCV_MSG_VALID);
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reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_CONTROL));
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reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_CONTROL, RCV_MSG_ACK, 1);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_CONTROL), reg);
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/*Wait for RCV_MSG_VALID to be 0*/
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reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_CONTROL));
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while (reg & mask) {
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if (timeout <= 0) {
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pr_err("RCV_MSG_VALID is not cleared\n");
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break;
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}
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mdelay(1);
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timeout -=1;
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reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_CONTROL));
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}
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}
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static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val)
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{
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u32 reg;
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reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_CONTROL));
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reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_CONTROL,
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TRN_MSG_VALID, val ? 1 : 0);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL),
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reg);
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}
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static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev,
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enum idh_event event)
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{
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u32 reg;
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u32 mask = REG_FIELD_MASK(BIF_BX_PF0_MAILBOX_CONTROL, RCV_MSG_VALID);
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if (event != IDH_FLR_NOTIFICATION_CMPL) {
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reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_CONTROL));
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if (!(reg & mask))
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return -ENOENT;
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}
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reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0));
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if (reg != event)
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return -ENOENT;
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xgpu_ai_mailbox_send_ack(adev);
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return 0;
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}
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static int xgpu_ai_poll_ack(struct amdgpu_device *adev)
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{
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int r = 0, timeout = AI_MAILBOX_TIMEDOUT;
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u32 mask = REG_FIELD_MASK(BIF_BX_PF0_MAILBOX_CONTROL, TRN_MSG_ACK);
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u32 reg;
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reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_CONTROL));
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while (!(reg & mask)) {
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if (timeout <= 0) {
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pr_err("Doesn't get ack from pf.\n");
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r = -ETIME;
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break;
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}
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mdelay(5);
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timeout -= 5;
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reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_CONTROL));
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}
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return r;
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}
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static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event)
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{
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int r = 0, timeout = AI_MAILBOX_TIMEDOUT;
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r = xgpu_ai_mailbox_rcv_msg(adev, event);
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while (r) {
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if (timeout <= 0) {
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pr_err("Doesn't get msg:%d from pf.\n", event);
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r = -ETIME;
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break;
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}
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mdelay(5);
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timeout -= 5;
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r = xgpu_ai_mailbox_rcv_msg(adev, event);
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}
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return r;
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}
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static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,
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enum idh_request req, u32 data1, u32 data2, u32 data3) {
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u32 reg;
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int r;
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reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0));
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reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0,
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MSGBUF_DATA, req);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),
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reg);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),
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data1);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),
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data2);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),
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data3);
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xgpu_ai_mailbox_set_valid(adev, true);
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/* start to poll ack */
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r = xgpu_ai_poll_ack(adev);
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if (r)
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pr_err("Doesn't get ack from pf, continue\n");
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xgpu_ai_mailbox_set_valid(adev, false);
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}
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static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
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enum idh_request req)
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{
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int r;
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xgpu_ai_mailbox_trans_msg(adev, req, 0, 0, 0);
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/* start to check msg if request is idh_req_gpu_init_access */
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if (req == IDH_REQ_GPU_INIT_ACCESS ||
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req == IDH_REQ_GPU_FINI_ACCESS ||
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req == IDH_REQ_GPU_RESET_ACCESS) {
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r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
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if (r) {
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pr_err("Doesn't get READY_TO_ACCESS_GPU from pf, give up\n");
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return r;
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}
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/* Retrieve checksum from mailbox2 */
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if (req == IDH_REQ_GPU_INIT_ACCESS) {
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adev->virt.fw_reserve.checksum_key =
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RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2));
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}
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}
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return 0;
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}
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static int xgpu_ai_request_reset(struct amdgpu_device *adev)
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{
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return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
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}
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static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev,
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bool init)
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{
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enum idh_request req;
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req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
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return xgpu_ai_send_access_requests(adev, req);
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}
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static int xgpu_ai_release_full_gpu_access(struct amdgpu_device *adev,
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bool init)
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{
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enum idh_request req;
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int r = 0;
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req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
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r = xgpu_ai_send_access_requests(adev, req);
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return r;
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}
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static int xgpu_ai_mailbox_ack_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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DRM_DEBUG("get ack intr and do nothing.\n");
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return 0;
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}
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static int xgpu_ai_set_mailbox_ack_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
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tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN,
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(state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
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return 0;
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}
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static void xgpu_ai_mailbox_flr_work(struct work_struct *work)
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{
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struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);
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struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);
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/* wait until RCV_MSG become 3 */
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if (xgpu_ai_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {
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pr_err("failed to recieve FLR_CMPL\n");
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return;
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}
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/* Trigger recovery due to world switch failure */
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amdgpu_sriov_gpu_reset(adev, NULL);
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}
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static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
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tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN,
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(state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
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return 0;
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}
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static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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int r;
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/* trigger gpu-reset by hypervisor only if TDR disbaled */
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if (amdgpu_lockup_timeout == 0) {
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/* see what event we get */
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r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
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/* only handle FLR_NOTIFY now */
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if (!r)
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schedule_work(&adev->virt.flr_work);
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}
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return 0;
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}
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static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_ack_irq_funcs = {
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.set = xgpu_ai_set_mailbox_ack_irq,
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.process = xgpu_ai_mailbox_ack_irq,
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};
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static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_rcv_irq_funcs = {
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.set = xgpu_ai_set_mailbox_rcv_irq,
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.process = xgpu_ai_mailbox_rcv_irq,
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};
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void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev)
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{
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adev->virt.ack_irq.num_types = 1;
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adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs;
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adev->virt.rcv_irq.num_types = 1;
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adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs;
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}
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int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev)
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{
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int r;
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r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);
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if (r)
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return r;
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r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);
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if (r) {
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amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
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return r;
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}
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return 0;
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}
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int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev)
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{
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int r;
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r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);
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if (r)
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return r;
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r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);
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if (r) {
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amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
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return r;
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}
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INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work);
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return 0;
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}
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void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev)
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{
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amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);
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amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
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}
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const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
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.req_full_gpu = xgpu_ai_request_full_gpu_access,
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.rel_full_gpu = xgpu_ai_release_full_gpu_access,
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.reset_gpu = xgpu_ai_request_reset,
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.trans_msg = xgpu_ai_mailbox_trans_msg,
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};
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