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2f7d63f909
The default for the Blackfin SPI driver is 8 bits and dma disabled, so many of the bfin5xx_spi_chip resources are redundant. So punt those parts. Further, drivers should themselves be declaring 16 bit transfers, so for those that do, and for the ones which no longer do 16 bit transfers, drop the bfin5xx_spi_chip resources. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
852 lines
20 KiB
C
852 lines
20 KiB
C
/*
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* Copyright 2004-20010 Analog Devices Inc.
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* 2005 National ICT Australia (NICTA)
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* Aidan Williams <aidan@nicta.com.au>
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/i2c.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/usb/musb.h>
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#include <linux/leds.h>
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#include <linux/input.h>
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#include <asm/dma.h>
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#include <asm/bfin5xx_spi.h>
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#include <asm/reboot.h>
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#include <asm/nand.h>
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#include <asm/portmux.h>
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#include <asm/dpmc.h>
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/*
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* Name the Board for the /proc/cpuinfo
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*/
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const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
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/*
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* Driver needs to know address, irq and flag pin.
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*/
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#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
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static struct resource musb_resources[] = {
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[0] = {
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.start = 0xffc03800,
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.end = 0xffc03cff,
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.flags = IORESOURCE_MEM,
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},
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[1] = { /* general IRQ */
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.start = IRQ_USB_INT0,
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.end = IRQ_USB_INT0,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
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},
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[2] = { /* DMA IRQ */
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.start = IRQ_USB_DMA,
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.end = IRQ_USB_DMA,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
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},
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};
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static struct musb_hdrc_config musb_config = {
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.multipoint = 0,
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.dyn_fifo = 0,
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.soft_con = 1,
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.dma = 1,
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.num_eps = 8,
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.dma_channels = 8,
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.gpio_vrsel = GPIO_PG13,
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/* Some custom boards need to be active low, just set it to "0"
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* if it is the case.
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*/
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.gpio_vrsel_active = 1,
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.clkin = 24, /* musb CLKIN in MHZ */
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};
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static struct musb_hdrc_platform_data musb_plat = {
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#if defined(CONFIG_USB_MUSB_OTG)
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.mode = MUSB_OTG,
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#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
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.mode = MUSB_HOST,
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#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
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.mode = MUSB_PERIPHERAL,
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#endif
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.config = &musb_config,
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};
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static u64 musb_dmamask = ~(u32)0;
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static struct platform_device musb_device = {
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.name = "musb-blackfin",
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.id = 0,
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.dev = {
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.dma_mask = &musb_dmamask,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &musb_plat,
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},
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.num_resources = ARRAY_SIZE(musb_resources),
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.resource = musb_resources,
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};
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#endif
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#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
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static struct resource bf52x_ra158z_resources[] = {
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{
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.start = IRQ_PPI_ERROR,
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.end = IRQ_PPI_ERROR,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device bf52x_ra158z_device = {
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.name = "bfin-ra158z",
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.id = -1,
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.num_resources = ARRAY_SIZE(bf52x_ra158z_resources),
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.resource = bf52x_ra158z_resources,
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};
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#endif
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#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
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static struct mtd_partition ad7160eval_partitions[] = {
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{
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.name = "bootloader(nor)",
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.size = 0x40000,
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.offset = 0,
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}, {
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.name = "linux kernel(nor)",
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.size = 0x1C0000,
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.offset = MTDPART_OFS_APPEND,
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}, {
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.name = "file system(nor)",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND,
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}
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};
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static struct physmap_flash_data ad7160eval_flash_data = {
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.width = 2,
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.parts = ad7160eval_partitions,
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.nr_parts = ARRAY_SIZE(ad7160eval_partitions),
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};
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static struct resource ad7160eval_flash_resource = {
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.start = 0x20000000,
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.end = 0x203fffff,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device ad7160eval_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &ad7160eval_flash_data,
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},
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.num_resources = 1,
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.resource = &ad7160eval_flash_resource,
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};
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#endif
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#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
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static struct mtd_partition partition_info[] = {
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{
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.name = "linux kernel(nand)",
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.offset = 0,
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.size = 4 * 1024 * 1024,
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},
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{
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.name = "file system(nand)",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct bf5xx_nand_platform bf5xx_nand_platform = {
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.data_width = NFC_NWIDTH_8,
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.partitions = partition_info,
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.nr_partitions = ARRAY_SIZE(partition_info),
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.rd_dly = 3,
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.wr_dly = 3,
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};
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static struct resource bf5xx_nand_resources[] = {
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{
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.start = NFC_CTL,
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.end = NFC_DATA_RD + 2,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = CH_NFC,
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.end = CH_NFC,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device bf5xx_nand_device = {
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.name = "bf5xx-nand",
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.id = 0,
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.num_resources = ARRAY_SIZE(bf5xx_nand_resources),
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.resource = bf5xx_nand_resources,
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.dev = {
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.platform_data = &bf5xx_nand_platform,
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},
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};
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#endif
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#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
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static struct platform_device rtc_device = {
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.name = "rtc-bfin",
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.id = -1,
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};
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#endif
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#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
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#include <linux/bfin_mac.h>
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static const unsigned short bfin_mac_peripherals[] = P_RMII0;
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static struct bfin_phydev_platform_data bfin_phydev_data[] = {
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{
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.addr = 1,
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.irq = IRQ_MAC_PHYINT,
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},
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};
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static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
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.phydev_number = 1,
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.phydev_data = bfin_phydev_data,
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.phy_mode = PHY_INTERFACE_MODE_RMII,
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.mac_peripherals = bfin_mac_peripherals,
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};
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static struct platform_device bfin_mii_bus = {
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.name = "bfin_mii_bus",
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.dev = {
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.platform_data = &bfin_mii_bus_data,
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}
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};
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static struct platform_device bfin_mac_device = {
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.name = "bfin_mac",
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.dev = {
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.platform_data = &bfin_mii_bus,
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}
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};
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#endif
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#if defined(CONFIG_MTD_M25P80) \
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|| defined(CONFIG_MTD_M25P80_MODULE)
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static struct mtd_partition bfin_spi_flash_partitions[] = {
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{
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.name = "bootloader(spi)",
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.size = 0x00040000,
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.offset = 0,
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.mask_flags = MTD_CAP_ROM
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}, {
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.name = "linux kernel(spi)",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND,
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}
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};
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static struct flash_platform_data bfin_spi_flash_data = {
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.name = "m25p80",
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.parts = bfin_spi_flash_partitions,
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.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
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.type = "m25p16",
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};
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/* SPI flash chip (m25p64) */
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static struct bfin5xx_spi_chip spi_flash_chip_info = {
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.enable_dma = 0, /* use dma transfer with this chip*/
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};
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#endif
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#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
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static struct bfin5xx_spi_chip mmc_spi_chip_info = {
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.enable_dma = 0,
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};
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#endif
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#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
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static struct platform_device bfin_i2s = {
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.name = "bfin-i2s",
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.id = CONFIG_SND_BF5XX_SPORT_NUM,
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/* TODO: add platform data here */
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};
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#endif
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#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
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static struct platform_device bfin_tdm = {
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.name = "bfin-tdm",
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.id = CONFIG_SND_BF5XX_SPORT_NUM,
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/* TODO: add platform data here */
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};
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#endif
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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#if defined(CONFIG_MTD_M25P80) \
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|| defined(CONFIG_MTD_M25P80_MODULE)
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{
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/* the modalias must be the same as spi device driver name */
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.modalias = "m25p80", /* Name of spi_driver for this device */
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.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0, /* Framework bus number */
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.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
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.platform_data = &bfin_spi_flash_data,
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.controller_data = &spi_flash_chip_info,
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.mode = SPI_MODE_3,
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},
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#endif
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#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
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|| defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
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{
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.modalias = "ad183x",
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.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 4,
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},
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#endif
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#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
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{
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.modalias = "mmc_spi",
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.max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = GPIO_PH3 + MAX_CTRL_CS,
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.controller_data = &mmc_spi_chip_info,
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.mode = SPI_MODE_3,
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},
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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{
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.modalias = "spidev",
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.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 1,
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},
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#endif
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};
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#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
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/* SPI controller data */
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static struct bfin5xx_spi_master bfin_spi0_info = {
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.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
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.enable_dma = 1, /* master has the ability to do dma transfer */
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.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
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};
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/* SPI (0) */
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static struct resource bfin_spi0_resource[] = {
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[0] = {
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.start = SPI0_REGBASE,
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.end = SPI0_REGBASE + 0xFF,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = CH_SPI,
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.end = CH_SPI,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = IRQ_SPI,
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.end = IRQ_SPI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device bfin_spi0_device = {
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.name = "bfin-spi",
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.id = 0, /* Bus number */
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.num_resources = ARRAY_SIZE(bfin_spi0_resource),
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.resource = bfin_spi0_resource,
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.dev = {
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.platform_data = &bfin_spi0_info, /* Passed to driver */
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},
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};
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#endif /* spi master and devices */
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#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
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#ifdef CONFIG_SERIAL_BFIN_UART0
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static struct resource bfin_uart0_resources[] = {
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{
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.start = UART0_THR,
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.end = UART0_GCTL+2,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_UART0_RX,
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.end = IRQ_UART0_RX+1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_UART0_ERROR,
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.end = IRQ_UART0_ERROR,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = CH_UART0_TX,
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.end = CH_UART0_TX,
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.flags = IORESOURCE_DMA,
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},
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{
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.start = CH_UART0_RX,
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.end = CH_UART0_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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static unsigned short bfin_uart0_peripherals[] = {
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P_UART0_TX, P_UART0_RX, 0
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};
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static struct platform_device bfin_uart0_device = {
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.name = "bfin-uart",
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.id = 0,
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.num_resources = ARRAY_SIZE(bfin_uart0_resources),
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.resource = bfin_uart0_resources,
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.dev = {
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.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
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},
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};
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART1
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static struct resource bfin_uart1_resources[] = {
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{
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.start = UART1_THR,
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.end = UART1_GCTL+2,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_UART1_RX,
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.end = IRQ_UART1_RX+1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_UART1_ERROR,
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.end = IRQ_UART1_ERROR,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = CH_UART1_TX,
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.end = CH_UART1_TX,
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.flags = IORESOURCE_DMA,
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},
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{
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.start = CH_UART1_RX,
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.end = CH_UART1_RX,
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.flags = IORESOURCE_DMA,
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},
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#ifdef CONFIG_BFIN_UART1_CTSRTS
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{ /* CTS pin */
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.start = GPIO_PF9,
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.end = GPIO_PF9,
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.flags = IORESOURCE_IO,
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},
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{ /* RTS pin */
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.start = GPIO_PF10,
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.end = GPIO_PF10,
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.flags = IORESOURCE_IO,
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},
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#endif
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};
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static unsigned short bfin_uart1_peripherals[] = {
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P_UART1_TX, P_UART1_RX, 0
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};
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static struct platform_device bfin_uart1_device = {
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.name = "bfin-uart",
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.id = 1,
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.num_resources = ARRAY_SIZE(bfin_uart1_resources),
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.resource = bfin_uart1_resources,
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.dev = {
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.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
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},
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};
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#endif
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#endif
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#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
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#ifdef CONFIG_BFIN_SIR0
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static struct resource bfin_sir0_resources[] = {
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{
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.start = 0xFFC00400,
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.end = 0xFFC004FF,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_UART0_RX,
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.end = IRQ_UART0_RX+1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = CH_UART0_RX,
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.end = CH_UART0_RX+1,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device bfin_sir0_device = {
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.name = "bfin_sir",
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|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
|
|
.resource = bfin_sir0_resources,
|
|
};
|
|
#endif
|
|
#ifdef CONFIG_BFIN_SIR1
|
|
static struct resource bfin_sir1_resources[] = {
|
|
{
|
|
.start = 0xFFC02000,
|
|
.end = 0xFFC020FF,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = IRQ_UART1_RX,
|
|
.end = IRQ_UART1_RX+1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = CH_UART1_RX,
|
|
.end = CH_UART1_RX+1,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
};
|
|
|
|
static struct platform_device bfin_sir1_device = {
|
|
.name = "bfin_sir",
|
|
.id = 1,
|
|
.num_resources = ARRAY_SIZE(bfin_sir1_resources),
|
|
.resource = bfin_sir1_resources,
|
|
};
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
|
|
#include <linux/input/ad7160.h>
|
|
static const struct ad7160_platform_data bfin_ad7160_ts_info = {
|
|
.sensor_x_res = 854,
|
|
.sensor_y_res = 480,
|
|
.pressure = 100,
|
|
.filter_coef = 3,
|
|
.coord_pref = AD7160_ORIG_TOP_LEFT,
|
|
.first_touch_window = 5,
|
|
.move_window = 3,
|
|
.event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID |
|
|
AD7160_EMIT_ABS_MT_PRESSURE |
|
|
AD7160_TRACKING_ID_ASCENDING,
|
|
.finger_act_ctrl = 0x64,
|
|
.haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) |
|
|
AD7160_HAPTIC_SLOT_A_LVL_HIGH |
|
|
AD7160_HAPTIC_SLOT_B(60) |
|
|
AD7160_HAPTIC_SLOT_B_LVL_LOW,
|
|
|
|
.haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) |
|
|
AD7160_HAPTIC_SLOT_A_LVL_HIGH |
|
|
AD7160_HAPTIC_SLOT_B(80) |
|
|
AD7160_HAPTIC_SLOT_B_LVL_LOW |
|
|
AD7160_HAPTIC_SLOT_C(120) |
|
|
AD7160_HAPTIC_SLOT_C_LVL_HIGH |
|
|
AD7160_HAPTIC_SLOT_D(30) |
|
|
AD7160_HAPTIC_SLOT_D_LVL_LOW,
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
|
|
static struct resource bfin_twi0_resource[] = {
|
|
[0] = {
|
|
.start = TWI0_REGBASE,
|
|
.end = TWI0_REGBASE,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = IRQ_TWI,
|
|
.end = IRQ_TWI,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device i2c_bfin_twi_device = {
|
|
.name = "i2c-bfin-twi",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
|
|
.resource = bfin_twi0_resource,
|
|
};
|
|
#endif
|
|
|
|
static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
|
|
#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
|
|
{
|
|
I2C_BOARD_INFO("ad7160", 0x33),
|
|
.irq = IRQ_PH1,
|
|
.platform_data = (void *)&bfin_ad7160_ts_info,
|
|
},
|
|
#endif
|
|
};
|
|
|
|
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
|
static struct resource bfin_sport0_uart_resources[] = {
|
|
{
|
|
.start = SPORT0_TCR1,
|
|
.end = SPORT0_MRCS3+4,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = IRQ_SPORT0_RX,
|
|
.end = IRQ_SPORT0_RX+1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = IRQ_SPORT0_ERROR,
|
|
.end = IRQ_SPORT0_ERROR,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static unsigned short bfin_sport0_peripherals[] = {
|
|
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
|
|
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
|
|
};
|
|
|
|
static struct platform_device bfin_sport0_uart_device = {
|
|
.name = "bfin-sport-uart",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
|
|
.resource = bfin_sport0_uart_resources,
|
|
.dev = {
|
|
.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
|
|
},
|
|
};
|
|
#endif
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
|
static struct resource bfin_sport1_uart_resources[] = {
|
|
{
|
|
.start = SPORT1_TCR1,
|
|
.end = SPORT1_MRCS3+4,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = IRQ_SPORT1_RX,
|
|
.end = IRQ_SPORT1_RX+1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = IRQ_SPORT1_ERROR,
|
|
.end = IRQ_SPORT1_ERROR,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static unsigned short bfin_sport1_peripherals[] = {
|
|
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
|
|
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
|
|
};
|
|
|
|
static struct platform_device bfin_sport1_uart_device = {
|
|
.name = "bfin-sport-uart",
|
|
.id = 1,
|
|
.num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
|
|
.resource = bfin_sport1_uart_resources,
|
|
.dev = {
|
|
.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
|
|
},
|
|
};
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
|
|
#include <asm/bfin_rotary.h>
|
|
|
|
static struct bfin_rotary_platform_data bfin_rotary_data = {
|
|
/*.rotary_up_key = KEY_UP,*/
|
|
/*.rotary_down_key = KEY_DOWN,*/
|
|
.rotary_rel_code = REL_WHEEL,
|
|
.rotary_button_key = KEY_ENTER,
|
|
.debounce = 10, /* 0..17 */
|
|
.mode = ROT_QUAD_ENC | ROT_DEBE,
|
|
};
|
|
|
|
static struct resource bfin_rotary_resources[] = {
|
|
{
|
|
.start = IRQ_CNT,
|
|
.end = IRQ_CNT,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device bfin_rotary_device = {
|
|
.name = "bfin-rotary",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(bfin_rotary_resources),
|
|
.resource = bfin_rotary_resources,
|
|
.dev = {
|
|
.platform_data = &bfin_rotary_data,
|
|
},
|
|
};
|
|
#endif
|
|
|
|
static const unsigned int cclk_vlev_datasheet[] = {
|
|
VRPAIR(VLEV_100, 400000000),
|
|
VRPAIR(VLEV_105, 426000000),
|
|
VRPAIR(VLEV_110, 500000000),
|
|
VRPAIR(VLEV_115, 533000000),
|
|
VRPAIR(VLEV_120, 600000000),
|
|
};
|
|
|
|
static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
|
|
.tuple_tab = cclk_vlev_datasheet,
|
|
.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
|
|
.vr_settling_time = 25 /* us */,
|
|
};
|
|
|
|
static struct platform_device bfin_dpmc = {
|
|
.name = "bfin dpmc",
|
|
.dev = {
|
|
.platform_data = &bfin_dmpc_vreg_data,
|
|
},
|
|
};
|
|
|
|
static struct platform_device *stamp_devices[] __initdata = {
|
|
|
|
&bfin_dpmc,
|
|
|
|
#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
|
|
&bf5xx_nand_device,
|
|
#endif
|
|
|
|
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
|
|
&rtc_device,
|
|
#endif
|
|
|
|
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
|
|
&musb_device,
|
|
#endif
|
|
|
|
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
|
|
&bfin_mii_bus,
|
|
&bfin_mac_device,
|
|
#endif
|
|
|
|
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
|
&bfin_spi0_device,
|
|
#endif
|
|
|
|
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
|
|
#ifdef CONFIG_SERIAL_BFIN_UART0
|
|
&bfin_uart0_device,
|
|
#endif
|
|
#ifdef CONFIG_SERIAL_BFIN_UART1
|
|
&bfin_uart1_device,
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
|
|
&bf52x_ra158z_device,
|
|
#endif
|
|
|
|
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
|
|
#ifdef CONFIG_BFIN_SIR0
|
|
&bfin_sir0_device,
|
|
#endif
|
|
#ifdef CONFIG_BFIN_SIR1
|
|
&bfin_sir1_device,
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
|
|
&i2c_bfin_twi_device,
|
|
#endif
|
|
|
|
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
|
&bfin_sport0_uart_device,
|
|
#endif
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
|
&bfin_sport1_uart_device,
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
|
|
&bfin_rotary_device,
|
|
#endif
|
|
|
|
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
|
|
&ad7160eval_flash_device,
|
|
#endif
|
|
|
|
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
|
|
&bfin_i2s,
|
|
#endif
|
|
|
|
#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
|
|
&bfin_tdm,
|
|
#endif
|
|
};
|
|
|
|
static int __init ad7160eval_init(void)
|
|
{
|
|
printk(KERN_INFO "%s(): registering device resources\n", __func__);
|
|
i2c_register_board_info(0, bfin_i2c_board_info,
|
|
ARRAY_SIZE(bfin_i2c_board_info));
|
|
platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
|
|
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(ad7160eval_init);
|
|
|
|
static struct platform_device *ad7160eval_early_devices[] __initdata = {
|
|
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
|
|
#ifdef CONFIG_SERIAL_BFIN_UART0
|
|
&bfin_uart0_device,
|
|
#endif
|
|
#ifdef CONFIG_SERIAL_BFIN_UART1
|
|
&bfin_uart1_device,
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
|
&bfin_sport0_uart_device,
|
|
#endif
|
|
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
|
&bfin_sport1_uart_device,
|
|
#endif
|
|
#endif
|
|
};
|
|
|
|
void __init native_machine_early_platform_add_devices(void)
|
|
{
|
|
printk(KERN_INFO "register early platform devices\n");
|
|
early_platform_add_devices(ad7160eval_early_devices,
|
|
ARRAY_SIZE(ad7160eval_early_devices));
|
|
}
|
|
|
|
void native_machine_restart(char *cmd)
|
|
{
|
|
/* workaround reboot hang when booting from SPI */
|
|
if ((bfin_read_SYSCR() & 0x7) == 0x3)
|
|
bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
|
|
}
|
|
|
|
void bfin_get_ether_addr(char *addr)
|
|
{
|
|
/* the MAC is stored in OTP memory page 0xDF */
|
|
u32 ret;
|
|
u64 otp_mac;
|
|
u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
|
|
|
|
ret = otp_read(0xDF, 0x00, &otp_mac);
|
|
if (!(ret & 0x1)) {
|
|
char *otp_mac_p = (char *)&otp_mac;
|
|
for (ret = 0; ret < 6; ++ret)
|
|
addr[ret] = otp_mac_p[5 - ret];
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(bfin_get_ether_addr);
|