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6c1652af61
The sama5d2 SoC has Synchronous Serial Controller which provides synchronous communication link with external devices. It's generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync. Signed-off-by: Alex Gershgorin <alex.gershgorin@qcore.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
1314 lines
30 KiB
Text
1314 lines
30 KiB
Text
/*
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* sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
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*
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* Copyright (C) 2015 Atmel,
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* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/at91.h>
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/ {
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model = "Atmel SAMA5D2 family SoC";
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compatible = "atmel,sama5d2";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &uart1;
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serial1 = &uart3;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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};
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pmu {
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compatible = "arm,cortex-a5-pmu";
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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etb {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0x740000 0x1000>;
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clocks = <&mck>;
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clock-names = "apb_pclk";
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port {
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etb_in: endpoint {
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slave-mode;
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remote-endpoint = <&etm_out>;
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};
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};
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};
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etm {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x73C000 0x1000>;
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clocks = <&mck>;
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clock-names = "apb_pclk";
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port {
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etm_out: endpoint {
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remote-endpoint = <&etb_in>;
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};
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};
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};
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memory {
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reg = <0x20000000 0x20000000>;
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};
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ns_sram: sram@00200000 {
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compatible = "mmio-sram";
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reg = <0x00200000 0x20000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usb0: gadget@00300000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "atmel,sama5d3-udc";
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reg = <0x00300000 0x100000
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0xfc02c000 0x400>;
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interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&udphs_clk>, <&utmi>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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ep@0 {
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reg = <0>;
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atmel,fifo-size = <64>;
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atmel,nb-banks = <1>;
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};
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ep@1 {
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reg = <1>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <3>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@2 {
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reg = <2>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <3>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@3 {
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reg = <3>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@4 {
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reg = <4>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@5 {
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reg = <5>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@6 {
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reg = <6>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@7 {
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reg = <7>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@8 {
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reg = <8>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@9 {
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reg = <9>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@10 {
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reg = <10>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@11 {
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reg = <11>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@12 {
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reg = <12>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@13 {
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reg = <13>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@14 {
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reg = <14>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@15 {
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reg = <15>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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};
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usb1: ohci@00400000 {
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compatible = "atmel,sama5d2-ohci", "usb-ohci";
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reg = <0x00400000 0x100000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
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clock-names = "ohci_clk", "hclk", "uhpck";
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status = "disabled";
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};
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usb2: ehci@00500000 {
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00500000 0x100000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&utmi>, <&uhphs_clk>;
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clock-names = "usb_clk", "ehci_clk";
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status = "disabled";
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};
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L2: cache-controller@00a00000 {
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compatible = "arm,pl310-cache";
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reg = <0x00a00000 0x1000>;
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interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
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cache-unified;
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cache-level = <2>;
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};
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nand0: nand@80000000 {
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compatible = "atmel,sama5d2-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = < /* EBI CS3 */
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0x80000000 0x08000000
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/* SMC PMECC regs */
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0xf8014070 0x00000490
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/* SMC PMECC Error Location regs */
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0xf8014500 0x00000200
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/* ROM Galois tables */
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0x00040000 0x00018000
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>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
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atmel,nand-addr-offset = <21>;
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atmel,nand-cmd-offset = <22>;
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atmel,nand-has-dma;
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atmel,has-pmecc;
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atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
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status = "disabled";
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nfc@c0000000 {
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compatible = "atmel,sama5d3-nfc";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = < /* NFC Command Registers */
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0xc0000000 0x08000000
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/* NFC HSMC regs */
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0xf8014000 0x00000070
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/* NFC SRAM banks */
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0x00100000 0x00100000
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>;
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clocks = <&hsmc_clk>;
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atmel,write-by-sram;
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};
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};
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sdmmc0: sdio-host@a0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xa0000000 0x300>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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sdmmc1: sdio-host@b0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xb0000000 0x300>;
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interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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hlcdc: hlcdc@f0000000 {
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compatible = "atmel,sama5d2-hlcdc";
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reg = <0xf0000000 0x2000>;
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interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
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clock-names = "periph_clk","sys_clk", "slow_clk";
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status = "disabled";
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hlcdc-display-controller {
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compatible = "atmel,hlcdc-display-controller";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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};
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hlcdc_pwm: hlcdc-pwm {
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compatible = "atmel,hlcdc-pwm";
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#pwm-cells = <3>;
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};
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};
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ramc0: ramc@f000c000 {
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compatible = "atmel,sama5d3-ddramc";
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reg = <0xf000c000 0x200>;
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clocks = <&ddrck>, <&mpddr_clk>;
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clock-names = "ddrck", "mpddr";
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};
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dma0: dma-controller@f0010000 {
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compatible = "atmel,sama5d4-dma";
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reg = <0xf0010000 0x1000>;
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interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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clocks = <&dma0_clk>;
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clock-names = "dma_clk";
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};
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/* Place dma1 here despite its address */
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dma1: dma-controller@f0004000 {
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compatible = "atmel,sama5d4-dma";
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reg = <0xf0004000 0x1000>;
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interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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clocks = <&dma1_clk>;
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clock-names = "dma_clk";
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};
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pmc: pmc@f0014000 {
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compatible = "atmel,sama5d2-pmc", "syscon";
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reg = <0xf0014000 0x160>;
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interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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main_rc_osc: main_rc_osc {
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compatible = "atmel,at91sam9x5-clk-main-rc-osc";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCRCS>;
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clock-frequency = <12000000>;
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clock-accuracy = <100000000>;
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};
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main_osc: main_osc {
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compatible = "atmel,at91rm9200-clk-main-osc";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCS>;
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clocks = <&main_xtal>;
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};
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main: mainck {
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compatible = "atmel,at91sam9x5-clk-main";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCSELS>;
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clocks = <&main_rc_osc &main_osc>;
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};
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plla: pllack {
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compatible = "atmel,sama5d3-clk-pll";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_LOCKA>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <12000000 12000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
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};
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plladiv: plladivck {
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compatible = "atmel,at91sam9x5-clk-plldiv";
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#clock-cells = <0>;
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clocks = <&plla>;
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};
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utmi: utmick {
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compatible = "atmel,at91sam9x5-clk-utmi";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_LOCKU>;
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clocks = <&main>;
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};
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mck: masterck {
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compatible = "atmel,at91sam9x5-clk-master";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MCKRDY>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
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atmel,clk-output-range = <124000000 166000000>;
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atmel,clk-divisors = <1 2 4 3>;
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};
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h32ck: h32mxck {
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#clock-cells = <0>;
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compatible = "atmel,sama5d4-clk-h32mx";
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clocks = <&mck>;
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};
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usb: usbck {
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compatible = "atmel,at91sam9x5-clk-usb";
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#clock-cells = <0>;
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clocks = <&plladiv>, <&utmi>;
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};
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prog: progck {
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compatible = "atmel,at91sam9x5-clk-programmable";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&pmc>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
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prog0: prog0 {
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#clock-cells = <0>;
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reg = <0>;
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interrupts = <AT91_PMC_PCKRDY(0)>;
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};
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prog1: prog1 {
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#clock-cells = <0>;
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reg = <1>;
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interrupts = <AT91_PMC_PCKRDY(1)>;
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};
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prog2: prog2 {
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#clock-cells = <0>;
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reg = <2>;
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interrupts = <AT91_PMC_PCKRDY(2)>;
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};
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};
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systemck {
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compatible = "atmel,at91rm9200-clk-system";
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#address-cells = <1>;
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#size-cells = <0>;
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ddrck: ddrck {
|
|
#clock-cells = <0>;
|
|
reg = <2>;
|
|
clocks = <&mck>;
|
|
};
|
|
|
|
lcdck: lcdck {
|
|
#clock-cells = <0>;
|
|
reg = <3>;
|
|
clocks = <&mck>;
|
|
};
|
|
|
|
uhpck: uhpck {
|
|
#clock-cells = <0>;
|
|
reg = <6>;
|
|
clocks = <&usb>;
|
|
};
|
|
|
|
udpck: udpck {
|
|
#clock-cells = <0>;
|
|
reg = <7>;
|
|
clocks = <&usb>;
|
|
};
|
|
|
|
pck0: pck0 {
|
|
#clock-cells = <0>;
|
|
reg = <8>;
|
|
clocks = <&prog0>;
|
|
};
|
|
|
|
pck1: pck1 {
|
|
#clock-cells = <0>;
|
|
reg = <9>;
|
|
clocks = <&prog1>;
|
|
};
|
|
|
|
pck2: pck2 {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
clocks = <&prog2>;
|
|
};
|
|
|
|
iscck: iscck {
|
|
#clock-cells = <0>;
|
|
reg = <18>;
|
|
clocks = <&mck>;
|
|
};
|
|
};
|
|
|
|
periph32ck {
|
|
compatible = "atmel,at91sam9x5-clk-peripheral";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&h32ck>;
|
|
|
|
macb0_clk: macb0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <5>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tdes_clk: tdes_clk {
|
|
#clock-cells = <0>;
|
|
reg = <11>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
matrix1_clk: matrix1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <14>;
|
|
};
|
|
|
|
hsmc_clk: hsmc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <17>;
|
|
};
|
|
|
|
pioA_clk: pioA_clk {
|
|
#clock-cells = <0>;
|
|
reg = <18>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx0_clk: flx0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <19>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx1_clk: flx1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <20>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx2_clk: flx2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <21>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx3_clk: flx3_clk {
|
|
#clock-cells = <0>;
|
|
reg = <22>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx4_clk: flx4_clk {
|
|
#clock-cells = <0>;
|
|
reg = <23>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart0_clk: uart0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <24>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart1_clk: uart1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <25>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart2_clk: uart2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <26>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart3_clk: uart3_clk {
|
|
#clock-cells = <0>;
|
|
reg = <27>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart4_clk: uart4_clk {
|
|
#clock-cells = <0>;
|
|
reg = <28>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
twi0_clk: twi0_clk {
|
|
reg = <29>;
|
|
#clock-cells = <0>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
twi1_clk: twi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <30>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
spi0_clk: spi0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <33>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
spi1_clk: spi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <34>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb0_clk: tcb0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <35>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb1_clk: tcb1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <36>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pwm_clk: pwm_clk {
|
|
#clock-cells = <0>;
|
|
reg = <38>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
adc_clk: adc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <40>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uhphs_clk: uhphs_clk {
|
|
#clock-cells = <0>;
|
|
reg = <41>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
udphs_clk: udphs_clk {
|
|
#clock-cells = <0>;
|
|
reg = <42>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
ssc0_clk: ssc0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <43>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
ssc1_clk: ssc1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <44>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
trng_clk: trng_clk {
|
|
#clock-cells = <0>;
|
|
reg = <47>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pdmic_clk: pdmic_clk {
|
|
#clock-cells = <0>;
|
|
reg = <48>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
securam_clk: securam_clk {
|
|
#clock-cells = <0>;
|
|
reg = <51>;
|
|
};
|
|
|
|
i2s0_clk: i2s0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <54>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
i2s1_clk: i2s1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <55>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
classd_clk: classd_clk {
|
|
#clock-cells = <0>;
|
|
reg = <59>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
};
|
|
|
|
periph64ck {
|
|
compatible = "atmel,at91sam9x5-clk-peripheral";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mck>;
|
|
|
|
dma0_clk: dma0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <6>;
|
|
};
|
|
|
|
dma1_clk: dma1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <7>;
|
|
};
|
|
|
|
aes_clk: aes_clk {
|
|
#clock-cells = <0>;
|
|
reg = <9>;
|
|
};
|
|
|
|
aesb_clk: aesb_clk {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
};
|
|
|
|
sha_clk: sha_clk {
|
|
#clock-cells = <0>;
|
|
reg = <12>;
|
|
};
|
|
|
|
mpddr_clk: mpddr_clk {
|
|
#clock-cells = <0>;
|
|
reg = <13>;
|
|
};
|
|
|
|
matrix0_clk: matrix0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <15>;
|
|
};
|
|
|
|
sdmmc0_hclk: sdmmc0_hclk {
|
|
#clock-cells = <0>;
|
|
reg = <31>;
|
|
};
|
|
|
|
sdmmc1_hclk: sdmmc1_hclk {
|
|
#clock-cells = <0>;
|
|
reg = <32>;
|
|
};
|
|
|
|
lcdc_clk: lcdc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <45>;
|
|
};
|
|
|
|
isc_clk: isc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <46>;
|
|
};
|
|
|
|
qspi0_clk: qspi0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <52>;
|
|
};
|
|
|
|
qspi1_clk: qspi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <53>;
|
|
};
|
|
};
|
|
|
|
gck {
|
|
compatible = "atmel,sama5d2-clk-generated";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
|
|
|
|
sdmmc0_gclk: sdmmc0_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <31>;
|
|
};
|
|
|
|
sdmmc1_gclk: sdmmc1_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <32>;
|
|
};
|
|
|
|
tcb0_gclk: tcb0_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <35>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb1_gclk: tcb1_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <36>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pwm_gclk: pwm_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <38>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pdmic_gclk: pdmic_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <48>;
|
|
};
|
|
|
|
i2s0_gclk: i2s0_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <54>;
|
|
};
|
|
|
|
i2s1_gclk: i2s1_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <55>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sha@f0028000 {
|
|
compatible = "atmel,at91sam9g46-sha";
|
|
reg = <0xf0028000 0x100>;
|
|
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(30))>;
|
|
dma-names = "tx";
|
|
clocks = <&sha_clk>;
|
|
clock-names = "sha_clk";
|
|
status = "okay";
|
|
};
|
|
|
|
aes@f002c000 {
|
|
compatible = "atmel,at91sam9g46-aes";
|
|
reg = <0xf002c000 0x100>;
|
|
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(26))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(27))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&aes_clk>;
|
|
clock-names = "aes_clk";
|
|
status = "okay";
|
|
};
|
|
|
|
spi0: spi@f8000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf8000000 0x100>;
|
|
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(6))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(7))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&spi0_clk>;
|
|
clock-names = "spi_clk";
|
|
atmel,fifo-size = <16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssc0: ssc@f8004000 {
|
|
compatible = "atmel,at91sam9g45-ssc";
|
|
reg = <0xf8004000 0x4000>;
|
|
interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(21))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(22))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&ssc0_clk>;
|
|
clock-names = "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
macb0: ethernet@f8008000 {
|
|
compatible = "atmel,sama5d2-gem";
|
|
reg = <0xf8008000 0x1000>;
|
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
|
|
66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
|
|
67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&macb0_clk>, <&macb0_clk>;
|
|
clock-names = "hclk", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
tcb0: timer@f800c000 {
|
|
compatible = "atmel,at91sam9x5-tcb";
|
|
reg = <0xf800c000 0x100>;
|
|
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&tcb0_clk>, <&clk32k>;
|
|
clock-names = "t0_clk", "slow_clk";
|
|
};
|
|
|
|
tcb1: timer@f8010000 {
|
|
compatible = "atmel,at91sam9x5-tcb";
|
|
reg = <0xf8010000 0x100>;
|
|
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&tcb1_clk>, <&clk32k>;
|
|
clock-names = "t0_clk", "slow_clk";
|
|
};
|
|
|
|
pdmic: pdmic@f8018000 {
|
|
compatible = "atmel,sama5d2-pdmic";
|
|
reg = <0xf8018000 0x124>;
|
|
interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
|
|
| AT91_XDMAC_DT_PERID(50))>;
|
|
dma-names = "rx";
|
|
clocks = <&pdmic_clk>, <&pdmic_gclk>;
|
|
clock-names = "pclk", "gclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@f801c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf801c000 0x100>;
|
|
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(35))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(36))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&uart0_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@f8020000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8020000 0x100>;
|
|
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(37))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(38))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&uart1_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@f8024000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8024000 0x100>;
|
|
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(39))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(40))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&uart2_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@f8028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xf8028000 0x100>;
|
|
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(0))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(1))>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi0_clk>;
|
|
atmel,fifo-size = <16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sfr: sfr@f8030000 {
|
|
compatible = "atmel,sama5d2-sfr", "syscon";
|
|
reg = <0xf8030000 0x98>;
|
|
};
|
|
|
|
flx0: flexcom@f8034000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xf8034000 0x200>;
|
|
clocks = <&flx0_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xf8034000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx1: flexcom@f8038000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xf8038000 0x200>;
|
|
clocks = <&flx1_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xf8038000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
securam: sram@f8044000 {
|
|
compatible = "atmel,sama5d2-securam", "mmio-sram";
|
|
reg = <0xf8044000 0x1420>;
|
|
clocks = <&securam_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0xf8044000 0x1420>;
|
|
};
|
|
|
|
rstc@f8048000 {
|
|
compatible = "atmel,sama5d3-rstc";
|
|
reg = <0xf8048000 0x10>;
|
|
clocks = <&clk32k>;
|
|
};
|
|
|
|
shdwc@f8048010 {
|
|
compatible = "atmel,sama5d2-shdwc";
|
|
reg = <0xf8048010 0x10>;
|
|
clocks = <&clk32k>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
atmel,wakeup-rtc-timer;
|
|
};
|
|
|
|
pit: timer@f8048030 {
|
|
compatible = "atmel,at91sam9260-pit";
|
|
reg = <0xf8048030 0x10>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
clocks = <&h32ck>;
|
|
};
|
|
|
|
watchdog@f8048040 {
|
|
compatible = "atmel,sama5d4-wdt";
|
|
reg = <0xf8048040 0x10>;
|
|
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&clk32k>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clk32k: sckc@f8048050 {
|
|
compatible = "atmel,sama5d4-sckc";
|
|
reg = <0xf8048050 0x4>;
|
|
|
|
clocks = <&slow_xtal>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
rtc@f80480b0 {
|
|
compatible = "atmel,at91rm9200-rtc";
|
|
reg = <0xf80480b0 0x30>;
|
|
interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&clk32k>;
|
|
};
|
|
|
|
spi1: spi@fc000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xfc000000 0x100>;
|
|
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(8))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(9))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&spi1_clk>;
|
|
clock-names = "spi_clk";
|
|
atmel,fifo-size = <16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@fc008000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc008000 0x100>;
|
|
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma1
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(41))>,
|
|
<&dma1
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(42))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&uart3_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@fc00c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc00c000 0x100>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(43))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(44))>;
|
|
dma-names = "tx", "rx";
|
|
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&uart4_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
flx2: flexcom@fc010000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc010000 0x200>;
|
|
clocks = <&flx2_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc010000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx3: flexcom@fc014000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc014000 0x200>;
|
|
clocks = <&flx3_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc014000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx4: flexcom@fc018000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc018000 0x200>;
|
|
clocks = <&flx4_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc018000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
trng@fc01c000 {
|
|
compatible = "atmel,at91sam9g45-trng";
|
|
reg = <0xfc01c000 0x100>;
|
|
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&trng_clk>;
|
|
};
|
|
|
|
aic: interrupt-controller@fc020000 {
|
|
#interrupt-cells = <3>;
|
|
compatible = "atmel,sama5d2-aic";
|
|
interrupt-controller;
|
|
reg = <0xfc020000 0x200>;
|
|
atmel,external-irqs = <49>;
|
|
};
|
|
|
|
i2c1: i2c@fc028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xfc028000 0x100>;
|
|
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(2))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(3))>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi1_clk>;
|
|
atmel,fifo-size = <16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc: adc@fc030000 {
|
|
compatible = "atmel,sama5d2-adc";
|
|
reg = <0xfc030000 0x100>;
|
|
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&adc_clk>;
|
|
clock-names = "adc_clk";
|
|
atmel,min-sample-rate-hz = <200000>;
|
|
atmel,max-sample-rate-hz = <20000000>;
|
|
atmel,startup-time-ms = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pioA: pinctrl@fc038000 {
|
|
compatible = "atmel,sama5d2-pinctrl";
|
|
reg = <0xfc038000 0x600>;
|
|
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<68 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<69 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<70 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
clocks = <&pioA_clk>;
|
|
};
|
|
|
|
secumod@fc040000 {
|
|
compatible = "atmel,sama5d2-secumod", "syscon";
|
|
reg = <0xfc040000 0x100>;
|
|
};
|
|
|
|
tdes@fc044000 {
|
|
compatible = "atmel,at91sam9g46-tdes";
|
|
reg = <0xfc044000 0x100>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(28))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(29))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&tdes_clk>;
|
|
clock-names = "tdes_clk";
|
|
status = "okay";
|
|
};
|
|
|
|
chipid@fc069000 {
|
|
compatible = "atmel,sama5d2-chipid";
|
|
reg = <0xfc069000 0x8>;
|
|
};
|
|
};
|
|
};
|
|
};
|