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![Jaswinder Singh Rajput](/assets/img/avatar_default.png)
Impact: Added AMD CPUs support Added flags for various AMD CPUs. Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
226 lines
7 KiB
C
Executable file
226 lines
7 KiB
C
Executable file
#ifndef _ASM_X86_CPU_DEBUG_H
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#define _ASM_X86_CPU_DEBUG_H
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/*
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* CPU x86 architecture debug
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*
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* Copyright(C) 2009 Jaswinder Singh Rajput
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*/
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/* Register flags */
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enum cpu_debug_bit {
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/* Model Specific Registers (MSRs) */
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CPU_MC_BIT, /* Machine Check */
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CPU_MONITOR_BIT, /* Monitor */
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CPU_TIME_BIT, /* Time */
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CPU_PMC_BIT, /* Performance Monitor */
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CPU_PLATFORM_BIT, /* Platform */
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CPU_APIC_BIT, /* APIC */
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CPU_POWERON_BIT, /* Power-on */
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CPU_CONTROL_BIT, /* Control */
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CPU_FEATURES_BIT, /* Features control */
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CPU_LBRANCH_BIT, /* Last Branch */
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CPU_BIOS_BIT, /* BIOS */
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CPU_FREQ_BIT, /* Frequency */
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CPU_MTTR_BIT, /* MTRR */
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CPU_PERF_BIT, /* Performance */
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CPU_CACHE_BIT, /* Cache */
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CPU_SYSENTER_BIT, /* Sysenter */
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CPU_THERM_BIT, /* Thermal */
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CPU_MISC_BIT, /* Miscellaneous */
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CPU_DEBUG_BIT, /* Debug */
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CPU_PAT_BIT, /* PAT */
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CPU_VMX_BIT, /* VMX */
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CPU_CALL_BIT, /* System Call */
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CPU_BASE_BIT, /* BASE Address */
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CPU_VER_BIT, /* Version ID */
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CPU_CONF_BIT, /* Configuration */
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CPU_SMM_BIT, /* System mgmt mode */
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CPU_SVM_BIT, /*Secure Virtual Machine*/
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CPU_OSVM_BIT, /* OS-Visible Workaround*/
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/* Standard Registers */
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CPU_TSS_BIT, /* Task Stack Segment */
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CPU_CR_BIT, /* Control Registers */
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CPU_DT_BIT, /* Descriptor Table */
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/* End of Registers flags */
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CPU_REG_ALL_BIT, /* Select all Registers */
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};
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#define CPU_REG_ALL (~0) /* Select all Registers */
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#define CPU_MC (1 << CPU_MC_BIT)
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#define CPU_MONITOR (1 << CPU_MONITOR_BIT)
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#define CPU_TIME (1 << CPU_TIME_BIT)
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#define CPU_PMC (1 << CPU_PMC_BIT)
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#define CPU_PLATFORM (1 << CPU_PLATFORM_BIT)
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#define CPU_APIC (1 << CPU_APIC_BIT)
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#define CPU_POWERON (1 << CPU_POWERON_BIT)
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#define CPU_CONTROL (1 << CPU_CONTROL_BIT)
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#define CPU_FEATURES (1 << CPU_FEATURES_BIT)
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#define CPU_LBRANCH (1 << CPU_LBRANCH_BIT)
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#define CPU_BIOS (1 << CPU_BIOS_BIT)
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#define CPU_FREQ (1 << CPU_FREQ_BIT)
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#define CPU_MTRR (1 << CPU_MTTR_BIT)
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#define CPU_PERF (1 << CPU_PERF_BIT)
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#define CPU_CACHE (1 << CPU_CACHE_BIT)
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#define CPU_SYSENTER (1 << CPU_SYSENTER_BIT)
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#define CPU_THERM (1 << CPU_THERM_BIT)
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#define CPU_MISC (1 << CPU_MISC_BIT)
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#define CPU_DEBUG (1 << CPU_DEBUG_BIT)
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#define CPU_PAT (1 << CPU_PAT_BIT)
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#define CPU_VMX (1 << CPU_VMX_BIT)
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#define CPU_CALL (1 << CPU_CALL_BIT)
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#define CPU_BASE (1 << CPU_BASE_BIT)
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#define CPU_VER (1 << CPU_VER_BIT)
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#define CPU_CONF (1 << CPU_CONF_BIT)
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#define CPU_SMM (1 << CPU_SMM_BIT)
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#define CPU_SVM (1 << CPU_SVM_BIT)
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#define CPU_OSVM (1 << CPU_OSVM_BIT)
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#define CPU_TSS (1 << CPU_TSS_BIT)
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#define CPU_CR (1 << CPU_CR_BIT)
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#define CPU_DT (1 << CPU_DT_BIT)
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/* Register file flags */
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enum cpu_file_bit {
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CPU_INDEX_BIT, /* index */
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CPU_VALUE_BIT, /* value */
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};
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#define CPU_FILE_VALUE (1 << CPU_VALUE_BIT)
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/*
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* DisplayFamily_DisplayModel Processor Families/Processor Number Series
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* -------------------------- ------------------------------------------
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* 05_01, 05_02, 05_04 Pentium, Pentium with MMX
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*
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* 06_01 Pentium Pro
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* 06_03, 06_05 Pentium II Xeon, Pentium II
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* 06_07, 06_08, 06_0A, 06_0B Pentium III Xeon, Pentum III
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*
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* 06_09, 060D Pentium M
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*
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* 06_0E Core Duo, Core Solo
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*
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* 06_0F Xeon 3000, 3200, 5100, 5300, 7300 series,
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* Core 2 Quad, Core 2 Extreme, Core 2 Duo,
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* Pentium dual-core
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* 06_17 Xeon 5200, 5400 series, Core 2 Quad Q9650
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*
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* 06_1C Atom
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*
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* 0F_00, 0F_01, 0F_02 Xeon, Xeon MP, Pentium 4
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* 0F_03, 0F_04 Xeon, Xeon MP, Pentium 4, Pentium D
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*
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* 0F_06 Xeon 7100, 5000 Series, Xeon MP,
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* Pentium 4, Pentium D
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*/
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/* Register processors bits */
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enum cpu_processor_bit {
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CPU_NONE,
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/* Intel */
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CPU_INTEL_PENTIUM_BIT,
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CPU_INTEL_P6_BIT,
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CPU_INTEL_PENTIUM_M_BIT,
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CPU_INTEL_CORE_BIT,
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CPU_INTEL_CORE2_BIT,
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CPU_INTEL_ATOM_BIT,
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CPU_INTEL_XEON_P4_BIT,
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CPU_INTEL_XEON_MP_BIT,
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/* AMD */
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CPU_AMD_K6_BIT,
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CPU_AMD_K7_BIT,
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CPU_AMD_K8_BIT,
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CPU_AMD_0F_BIT,
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CPU_AMD_10_BIT,
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CPU_AMD_11_BIT,
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};
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#define CPU_INTEL_PENTIUM (1 << CPU_INTEL_PENTIUM_BIT)
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#define CPU_INTEL_P6 (1 << CPU_INTEL_P6_BIT)
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#define CPU_INTEL_PENTIUM_M (1 << CPU_INTEL_PENTIUM_M_BIT)
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#define CPU_INTEL_CORE (1 << CPU_INTEL_CORE_BIT)
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#define CPU_INTEL_CORE2 (1 << CPU_INTEL_CORE2_BIT)
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#define CPU_INTEL_ATOM (1 << CPU_INTEL_ATOM_BIT)
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#define CPU_INTEL_XEON_P4 (1 << CPU_INTEL_XEON_P4_BIT)
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#define CPU_INTEL_XEON_MP (1 << CPU_INTEL_XEON_MP_BIT)
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#define CPU_INTEL_PX (CPU_INTEL_P6 | CPU_INTEL_PENTIUM_M)
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#define CPU_INTEL_COREX (CPU_INTEL_CORE | CPU_INTEL_CORE2)
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#define CPU_INTEL_XEON (CPU_INTEL_XEON_P4 | CPU_INTEL_XEON_MP)
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#define CPU_CO_AT (CPU_INTEL_CORE | CPU_INTEL_ATOM)
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#define CPU_C2_AT (CPU_INTEL_CORE2 | CPU_INTEL_ATOM)
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#define CPU_CX_AT (CPU_INTEL_COREX | CPU_INTEL_ATOM)
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#define CPU_CX_XE (CPU_INTEL_COREX | CPU_INTEL_XEON)
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#define CPU_P6_XE (CPU_INTEL_P6 | CPU_INTEL_XEON)
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#define CPU_PM_CO_AT (CPU_INTEL_PENTIUM_M | CPU_CO_AT)
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#define CPU_C2_AT_XE (CPU_C2_AT | CPU_INTEL_XEON)
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#define CPU_CX_AT_XE (CPU_CX_AT | CPU_INTEL_XEON)
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#define CPU_P6_CX_AT (CPU_INTEL_P6 | CPU_CX_AT)
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#define CPU_P6_CX_XE (CPU_P6_XE | CPU_INTEL_COREX)
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#define CPU_P6_CX_AT_XE (CPU_INTEL_P6 | CPU_CX_AT_XE)
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#define CPU_PM_CX_AT_XE (CPU_INTEL_PENTIUM_M | CPU_CX_AT_XE)
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#define CPU_PM_CX_AT (CPU_INTEL_PENTIUM_M | CPU_CX_AT)
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#define CPU_PM_CX_XE (CPU_INTEL_PENTIUM_M | CPU_CX_XE)
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#define CPU_PX_CX_AT (CPU_INTEL_PX | CPU_CX_AT)
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#define CPU_PX_CX_AT_XE (CPU_INTEL_PX | CPU_CX_AT_XE)
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/* Select all supported Intel CPUs */
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#define CPU_INTEL_ALL (CPU_INTEL_PENTIUM | CPU_PX_CX_AT_XE)
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#define CPU_AMD_K6 (1 << CPU_AMD_K6_BIT)
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#define CPU_AMD_K7 (1 << CPU_AMD_K7_BIT)
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#define CPU_AMD_K8 (1 << CPU_AMD_K8_BIT)
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#define CPU_AMD_0F (1 << CPU_AMD_0F_BIT)
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#define CPU_AMD_10 (1 << CPU_AMD_10_BIT)
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#define CPU_AMD_11 (1 << CPU_AMD_11_BIT)
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#define CPU_K10_PLUS (CPU_AMD_10 | CPU_AMD_11)
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#define CPU_K0F_PLUS (CPU_AMD_0F | CPU_K10_PLUS)
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#define CPU_K8_PLUS (CPU_AMD_K8 | CPU_K0F_PLUS)
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#define CPU_K7_PLUS (CPU_AMD_K7 | CPU_K8_PLUS)
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/* Select all supported AMD CPUs */
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#define CPU_AMD_ALL (CPU_AMD_K6 | CPU_K7_PLUS)
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/* Select all supported CPUs */
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#define CPU_ALL (CPU_INTEL_ALL | CPU_AMD_ALL)
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#define MAX_CPU_FILES 512
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struct cpu_private {
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unsigned cpu;
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unsigned type;
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unsigned reg;
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unsigned file;
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};
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struct cpu_debug_base {
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char *name; /* Register name */
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unsigned flag; /* Register flag */
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unsigned write; /* Register write flag */
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};
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/*
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* Currently it looks similar to cpu_debug_base but once we add more files
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* cpu_file_base will go in different direction
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*/
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struct cpu_file_base {
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char *name; /* Register file name */
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unsigned flag; /* Register file flag */
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unsigned write; /* Register write flag */
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};
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struct cpu_cpuX_base {
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struct dentry *dentry; /* Register dentry */
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int init; /* Register index file */
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};
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struct cpu_debug_range {
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unsigned min; /* Register range min */
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unsigned max; /* Register range max */
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unsigned flag; /* Supported flags */
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unsigned model; /* Supported models */
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};
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#endif /* _ASM_X86_CPU_DEBUG_H */
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