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35b137630f
VPU stands for Versatile Processing Unit and it's a CPU-integrated
inference accelerator for Computer Vision and Deep Learning
applications.
The VPU device consist of following components:
- Buttress - provides CPU to VPU integration, interrupt, frequency and
power management.
- Memory Management Unit (based on ARM MMU-600) - translates VPU to
host DMA addresses, isolates user workloads.
- RISC based microcontroller - executes firmware that provides job
execution API for the kernel-mode driver
- Neural Compute Subsystem (NCS) - does the actual work, provides
Compute and Copy engines.
- Network on Chip (NoC) - network fabric connecting all the components
This driver supports VPU IP v2.7 integrated into Intel Meteor Lake
client CPUs (14th generation).
Module sources are at drivers/accel/ivpu and module name is
"intel_vpu.ko".
This patch includes only very besic functionality:
- module, PCI device and IRQ initialization
- register definitions and low level register manipulation functions
- SET/GET_PARAM ioctls
- power up without firmware
Co-developed-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com>
Signed-off-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20230117092723.60441-2-jacek.lawrynowicz@linux.intel.com
115 lines
3.8 KiB
C
115 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020-2023 Intel Corporation
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*/
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#ifndef __IVPU_HW_REG_IO_H__
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#define __IVPU_HW_REG_IO_H__
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#include <linux/bitfield.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include "ivpu_drv.h"
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#define REG_POLL_SLEEP_US 50
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#define REG_IO_ERROR 0xffffffff
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#define REGB_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regb, (reg), #reg, __func__)
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#define REGB_RD32_SILENT(reg) readl(vdev->regb + (reg))
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#define REGB_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regb, (reg), #reg, __func__)
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#define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__)
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#define REGB_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regb, (reg), (val), #reg, __func__)
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#define REGV_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regv, (reg), #reg, __func__)
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#define REGV_RD32_SILENT(reg) readl(vdev->regv + (reg))
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#define REGV_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regv, (reg), #reg, __func__)
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#define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__)
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#define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__)
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#define REGV_WR32I(reg, stride, index, val) \
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ivpu_hw_reg_wr32_index(vdev, vdev->regv, (reg), (stride), (index), (val), #reg, __func__)
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#define REG_FLD(REG, FLD) \
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(REG##_##FLD##_MASK)
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#define REG_FLD_NUM(REG, FLD, num) \
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FIELD_PREP(REG##_##FLD##_MASK, num)
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#define REG_GET_FLD(REG, FLD, val) \
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FIELD_GET(REG##_##FLD##_MASK, val)
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#define REG_CLR_FLD(REG, FLD, val) \
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((val) & ~(REG##_##FLD##_MASK))
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#define REG_SET_FLD(REG, FLD, val) \
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((val) | (REG##_##FLD##_MASK))
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#define REG_SET_FLD_NUM(REG, FLD, num, val) \
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(((val) & ~(REG##_##FLD##_MASK)) | FIELD_PREP(REG##_##FLD##_MASK, num))
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#define REG_TEST_FLD(REG, FLD, val) \
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((REG##_##FLD##_MASK) == ((val) & (REG##_##FLD##_MASK)))
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#define REG_TEST_FLD_NUM(REG, FLD, num, val) \
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((num) == FIELD_GET(REG##_##FLD##_MASK, val))
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#define REGB_POLL(reg, var, cond, timeout_us) \
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read_poll_timeout(REGB_RD32_SILENT, var, cond, REG_POLL_SLEEP_US, timeout_us, false, reg)
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#define REGV_POLL(reg, var, cond, timeout_us) \
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read_poll_timeout(REGV_RD32_SILENT, var, cond, REG_POLL_SLEEP_US, timeout_us, false, reg)
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#define REGB_POLL_FLD(reg, fld, val, timeout_us) \
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({ \
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u32 var; \
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REGB_POLL(reg, var, (FIELD_GET(reg##_##fld##_MASK, var) == (val)), timeout_us); \
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})
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#define REGV_POLL_FLD(reg, fld, val, timeout_us) \
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({ \
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u32 var; \
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REGV_POLL(reg, var, (FIELD_GET(reg##_##fld##_MASK, var) == (val)), timeout_us); \
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})
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static inline u32
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ivpu_hw_reg_rd32(struct ivpu_device *vdev, void __iomem *base, u32 reg,
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const char *name, const char *func)
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{
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u32 val = readl(base + reg);
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ivpu_dbg(vdev, REG, "%s RD: %s (0x%08x) => 0x%08x\n", func, name, reg, val);
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return val;
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}
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static inline u64
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ivpu_hw_reg_rd64(struct ivpu_device *vdev, void __iomem *base, u32 reg,
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const char *name, const char *func)
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{
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u64 val = readq(base + reg);
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ivpu_dbg(vdev, REG, "%s RD: %s (0x%08x) => 0x%016llx\n", func, name, reg, val);
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return val;
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}
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static inline void
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ivpu_hw_reg_wr32(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 val,
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const char *name, const char *func)
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{
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ivpu_dbg(vdev, REG, "%s WR: %s (0x%08x) <= 0x%08x\n", func, name, reg, val);
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writel(val, base + reg);
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}
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static inline void
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ivpu_hw_reg_wr64(struct ivpu_device *vdev, void __iomem *base, u32 reg, u64 val,
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const char *name, const char *func)
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{
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ivpu_dbg(vdev, REG, "%s WR: %s (0x%08x) <= 0x%016llx\n", func, name, reg, val);
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writeq(val, base + reg);
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}
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static inline void
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ivpu_hw_reg_wr32_index(struct ivpu_device *vdev, void __iomem *base, u32 reg,
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u32 stride, u32 index, u32 val, const char *name,
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const char *func)
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{
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reg += index * stride;
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ivpu_dbg(vdev, REG, "%s WR: %s_%d (0x%08x) <= 0x%08x\n", func, name, index, reg, val);
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writel(val, base + reg);
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}
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#endif /* __IVPU_HW_REG_IO_H__ */
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