Claudiu Beznea 9570ae0e1d clk: renesas: rzg2l: Check reset monitor registers ... [ Upstream commit da235d2fac ] The hardware manual of both RZ/G2L and RZ/G3S specifies that the reset monitor registers need to be interrogated when the reset signals are toggled (chapters "Procedures for Supplying and Stopping Reset Signals" and "Procedure for Activating Modules"). Without this, there is a chance that different modules (e.g. Ethernet) are not ready after their reset signal is toggled, leading to failures (on probe or resume from deep sleep states). The same indications are available for RZ/V2M for TYPE-B reset controls. Fixes: ef3c613ccd ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Fixes: 8090bea324 ("clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org>		2024-01-25 15:27:35 -08:00
..
clk-div6.c
clk-div6.h
clk-emev2.c
clk-mstp.c
clk-r8a73a4.c
clk-r8a7740.c
clk-r8a7778.c
clk-r8a7779.c
clk-rz.c
clk-sh73a0.c
Kconfig	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	2023-03-17 08:50:30 +01:00
Makefile
r7s9210-cpg-mssr.c
r8a774a1-cpg-mssr.c
r8a774b1-cpg-mssr.c
r8a774c0-cpg-mssr.c
r8a774e1-cpg-mssr.c
r8a779a0-cpg-mssr.c	clk: renesas: r8a779a0: Fix SD0H clock name	2022-12-31 13:32:05 +01:00
r8a779f0-cpg-mssr.c	clk: renesas: r8a779f0: Fix SCIF parent clocks	2022-12-31 13:32:09 +01:00
r8a779g0-cpg-mssr.c	clk: renesas: r8a779g0: Fix HSCIF parent clocks	2022-10-26 12:05:36 +02:00
r8a7742-cpg-mssr.c
r8a7743-cpg-mssr.c
r8a7745-cpg-mssr.c
r8a7790-cpg-mssr.c
r8a7791-cpg-mssr.c
r8a7792-cpg-mssr.c
r8a7794-cpg-mssr.c
r8a7795-cpg-mssr.c	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	2023-03-17 08:50:30 +01:00
r8a7796-cpg-mssr.c
r8a77470-cpg-mssr.c
r8a77965-cpg-mssr.c
r8a77970-cpg-mssr.c
r8a77980-cpg-mssr.c
r8a77990-cpg-mssr.c
r8a77995-cpg-mssr.c
r9a06g032-clocks.c	clk: renesas: r9a06g032: Repair grave increment error	2022-12-31 13:32:06 +01:00
r9a07g043-cpg.c
r9a07g044-cpg.c	clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info	2022-08-22 09:47:36 +02:00
r9a09g011-cpg.c	clk: renesas: r9a09g011: Add IIC clock and reset entries	2022-08-29 09:22:57 +02:00
rcar-cpg-lib.c	clk: renesas: rcar-gen3: Extend SDnH divider table	2023-11-20 11:51:56 +01:00
rcar-cpg-lib.h
rcar-gen2-cpg.c
rcar-gen2-cpg.h
rcar-gen3-cpg.c	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	2023-03-17 08:50:30 +01:00
rcar-gen3-cpg.h
rcar-gen4-cpg.c
rcar-gen4-cpg.h
rcar-usb2-clock-sel.c
renesas-cpg-mssr.c	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	2023-03-17 08:50:30 +01:00
renesas-cpg-mssr.h	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	2023-03-17 08:50:30 +01:00
rzg2l-cpg.c	clk: renesas: rzg2l: Check reset monitor registers	2024-01-25 15:27:35 -08:00
rzg2l-cpg.h	clk: renesas: rzg2l: Lock around writes to mux register	2023-11-20 11:51:56 +01:00