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b56bae2dd6
Add a reset controller to PolarFire SoC's clock driver. This reset controller is registered as an aux device and read/write functions exported to the drivers namespace so that the reset controller can access the peripheral device reset register. Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909123123.2699583-5-conor.dooley@microchip.com
51 lines
1 KiB
C
51 lines
1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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*
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* Microchip PolarFire SoC (MPFS)
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*
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* Copyright (c) 2020 Microchip Corporation. All rights reserved.
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*
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* Author: Conor Dooley <conor.dooley@microchip.com>
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*
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*/
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#ifndef __SOC_MPFS_H__
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#define __SOC_MPFS_H__
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#include <linux/types.h>
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#include <linux/of_device.h>
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struct mpfs_sys_controller;
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struct mpfs_mss_msg {
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u8 cmd_opcode;
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u16 cmd_data_size;
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struct mpfs_mss_response *response;
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u8 *cmd_data;
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u16 mbox_offset;
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u16 resp_offset;
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};
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struct mpfs_mss_response {
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u32 resp_status;
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u32 *resp_msg;
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u16 resp_size;
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};
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#if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL)
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int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, struct mpfs_mss_msg *msg);
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struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev);
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#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
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#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
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u32 mpfs_reset_read(struct device *dev);
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void mpfs_reset_write(struct device *dev, u32 val);
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#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */
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#endif /* __SOC_MPFS_H__ */
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