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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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b3df895aeb
This adds support kexec on FSL-BookE where the MMU can not be simply switched off. The code borrows the initial MMU-setup code to create the identical mapping mapping. The only difference to the original boot code is the size of the mapping(s) and the executeable address. The kexec code maps the first 2 GiB of memory in 256 MiB steps. This should work also on e500v1 boxes. SMP support is still not available. (Kumar: Added minor change to build to ifdef CONFIG_PPC_STD_MMU_64 some code that was PPC64 specific) Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
237 lines
5.5 KiB
ArmAsm
237 lines
5.5 KiB
ArmAsm
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/* 1. Find the index of the entry we're executing in */
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bl invstr /* Find our address */
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invstr: mflr r6 /* Make it accessible */
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mfmsr r7
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rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
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mfspr r7, SPRN_PID0
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slwi r7,r7,16
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or r7,r7,r4
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mtspr SPRN_MAS6,r7
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tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
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mfspr r7,SPRN_MAS1
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andis. r7,r7,MAS1_VALID@h
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bne match_TLB
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mfspr r7,SPRN_MMUCFG
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rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
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cmpwi r7,3
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bne match_TLB /* skip if NPIDS != 3 */
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mfspr r7,SPRN_PID1
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slwi r7,r7,16
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or r7,r7,r4
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mtspr SPRN_MAS6,r7
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tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
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mfspr r7,SPRN_MAS1
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andis. r7,r7,MAS1_VALID@h
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bne match_TLB
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mfspr r7, SPRN_PID2
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slwi r7,r7,16
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or r7,r7,r4
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mtspr SPRN_MAS6,r7
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tlbsx 0,r6 /* Fall through, we had to match */
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match_TLB:
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mfspr r7,SPRN_MAS0
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rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
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mfspr r7,SPRN_MAS1 /* Insure IPROT set */
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oris r7,r7,MAS1_IPROT@h
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mtspr SPRN_MAS1,r7
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tlbwe
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/* 2. Invalidate all entries except the entry we're executing in */
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mfspr r9,SPRN_TLB1CFG
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andi. r9,r9,0xfff
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li r6,0 /* Set Entry counter to 0 */
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1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
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rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
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mtspr SPRN_MAS0,r7
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tlbre
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mfspr r7,SPRN_MAS1
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rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
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cmpw r3,r6
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beq skpinv /* Dont update the current execution TLB */
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mtspr SPRN_MAS1,r7
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tlbwe
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isync
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skpinv: addi r6,r6,1 /* Increment */
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cmpw r6,r9 /* Are we done? */
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bne 1b /* If not, repeat */
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/* Invalidate TLB0 */
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li r6,0x04
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tlbivax 0,r6
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TLBSYNC
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/* Invalidate TLB1 */
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li r6,0x0c
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tlbivax 0,r6
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TLBSYNC
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/* 3. Setup a temp mapping and jump to it */
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andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
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addi r5, r5, 0x1
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lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
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rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
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mtspr SPRN_MAS0,r7
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tlbre
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/* grab and fixup the RPN */
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mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
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rlwinm r6,r6,25,27,31
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li r8,-1
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addi r6,r6,10
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slw r6,r8,r6 /* convert to mask */
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bl 1f /* Find our address */
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1: mflr r7
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mfspr r8,SPRN_MAS3
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#ifdef CONFIG_PHYS_64BIT
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mfspr r23,SPRN_MAS7
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#endif
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and r8,r6,r8
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subfic r9,r6,-4096
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and r9,r9,r7
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or r25,r8,r9
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ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
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/* Just modify the entry ID and EPN for the temp mapping */
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lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
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rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
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mtspr SPRN_MAS0,r7
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xori r6,r4,1 /* Setup TMP mapping in the other Address space */
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slwi r6,r6,12
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oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
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ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
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mtspr SPRN_MAS1,r6
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mfspr r6,SPRN_MAS2
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li r7,0 /* temp EPN = 0 */
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rlwimi r7,r6,0,20,31
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mtspr SPRN_MAS2,r7
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mtspr SPRN_MAS3,r8
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tlbwe
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xori r6,r4,1
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slwi r6,r6,5 /* setup new context with other address space */
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bl 1f /* Find our address */
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1: mflr r9
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rlwimi r7,r9,0,20,31
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addi r7,r7,(2f - 1b)
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mtspr SPRN_SRR0,r7
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mtspr SPRN_SRR1,r6
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rfi
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2:
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/* 4. Clear out PIDs & Search info */
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li r6,0
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mtspr SPRN_MAS6,r6
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mtspr SPRN_PID0,r6
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mfspr r7,SPRN_MMUCFG
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rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
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cmpwi r7,3
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bne 2f /* skip if NPIDS != 3 */
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mtspr SPRN_PID1,r6
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mtspr SPRN_PID2,r6
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/* 5. Invalidate mapping we started in */
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2:
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lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
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rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
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mtspr SPRN_MAS0,r7
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tlbre
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mfspr r6,SPRN_MAS1
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rlwinm r6,r6,0,2,0 /* clear IPROT */
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mtspr SPRN_MAS1,r6
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tlbwe
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/* Invalidate TLB1 */
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li r9,0x0c
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tlbivax 0,r9
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TLBSYNC
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/* The mapping only needs to be cache-coherent on SMP */
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#ifdef CONFIG_SMP
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#define M_IF_SMP MAS2_M
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#else
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#define M_IF_SMP 0
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#endif
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#if defined(ENTRY_MAPPING_BOOT_SETUP)
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/* 6. Setup KERNELBASE mapping in TLB1[0] */
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lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
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mtspr SPRN_MAS0,r6
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lis r6,(MAS1_VALID|MAS1_IPROT)@h
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ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
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mtspr SPRN_MAS1,r6
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lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
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ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
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mtspr SPRN_MAS2,r6
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mtspr SPRN_MAS3,r8
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tlbwe
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/* 7. Jump to KERNELBASE mapping */
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lis r6,(KERNELBASE & ~0xfff)@h
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ori r6,r6,(KERNELBASE & ~0xfff)@l
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#elif defined(ENTRY_MAPPING_KEXEC_SETUP)
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/*
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* 6. Setup a 1:1 mapping in TLB1. Esel 0 is unsued, 1 or 2 contains the tmp
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* mapping so we start at 3. We setup 8 mappings, each 256MiB in size. This
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* will cover the first 2GiB of memory.
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*/
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lis r10, (MAS1_VALID|MAS1_IPROT)@h
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ori r10,r10, (MAS1_TSIZE(BOOK3E_PAGESZ_256M))@l
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li r11, 0
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li r0, 8
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mtctr r0
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next_tlb_setup:
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addi r0, r11, 3
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rlwinm r0, r0, 16, 4, 15 // Compute esel
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rlwinm r9, r11, 28, 0, 3 // Compute [ER]PN
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oris r0, r0, (MAS0_TLBSEL(1))@h
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mtspr SPRN_MAS0,r0
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mtspr SPRN_MAS1,r10
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mtspr SPRN_MAS2,r9
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ori r9, r9, (MAS3_SX|MAS3_SW|MAS3_SR)
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mtspr SPRN_MAS3,r9
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tlbwe
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addi r11, r11, 1
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bdnz+ next_tlb_setup
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/* 7. Jump to our 1:1 mapping */
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li r6, 0
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#else
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#error You need to specify the mapping or not use this at all.
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#endif
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lis r7,MSR_KERNEL@h
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ori r7,r7,MSR_KERNEL@l
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bl 1f /* Find our address */
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1: mflr r9
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rlwimi r6,r9,0,20,31
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addi r6,r6,(2f - 1b)
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add r6, r6, r25
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mtspr SPRN_SRR0,r6
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mtspr SPRN_SRR1,r7
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rfi /* start execution out of TLB1[0] entry */
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/* 8. Clear out the temp mapping */
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2: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
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rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
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mtspr SPRN_MAS0,r7
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tlbre
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mfspr r8,SPRN_MAS1
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rlwinm r8,r8,0,2,0 /* clear IPROT */
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mtspr SPRN_MAS1,r8
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tlbwe
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/* Invalidate TLB1 */
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li r9,0x0c
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tlbivax 0,r9
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TLBSYNC
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