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a96cbb146a
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5 Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx Signed-off-by: Stephen Boyd <sboyd@kernel.org>
471 lines
12 KiB
C
471 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,sm8450-videocc.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "gdsc.h"
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#include "reset.h"
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enum {
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DT_BI_TCXO,
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};
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enum {
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P_BI_TCXO,
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P_VIDEO_CC_PLL0_OUT_MAIN,
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P_VIDEO_CC_PLL1_OUT_MAIN,
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};
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static const struct pll_vco lucid_ole_vco[] = {
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{ 249600000, 2300000000, 0 },
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};
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static const struct alpha_pll_config video_cc_pll0_config = {
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/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
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.l = 0x44440025,
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.alpha = 0x8000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll video_cc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_pll0",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
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};
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static const struct alpha_pll_config video_cc_pll1_config = {
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/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
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.l = 0x44440036,
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.alpha = 0xb000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll video_cc_pll1 = {
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.offset = 0x1000,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_pll1",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
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};
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static const struct parent_map video_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
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};
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static const struct clk_parent_data video_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &video_cc_pll0.clkr.hw },
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};
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static const struct parent_map video_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
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};
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static const struct clk_parent_data video_cc_parent_data_1[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &video_cc_pll1.clkr.hw },
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};
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static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
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F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_mvs0_clk_src = {
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.cmd_rcgr = 0x8000,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_0,
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.freq_tbl = ftbl_video_cc_mvs0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_clk_src",
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.parent_data = video_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
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F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
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F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
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F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
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F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_mvs1_clk_src = {
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.cmd_rcgr = 0x8018,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_1,
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.freq_tbl = ftbl_video_cc_mvs1_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs1_clk_src",
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.parent_data = video_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
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.reg = 0x80c4,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_div_clk_src",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
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.reg = 0x8070,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0c_div2_div_clk_src",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
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.reg = 0x80ec,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs1_div_clk_src",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
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.reg = 0x809c,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs1c_div2_div_clk_src",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_branch video_cc_mvs0_clk = {
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.halt_reg = 0x80b8,
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.halt_check = BRANCH_HALT_SKIP,
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.hwcg_reg = 0x80b8,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x80b8,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0c_clk = {
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.halt_reg = 0x8064,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x8064,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0c_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs1_clk = {
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.halt_reg = 0x80e0,
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.halt_check = BRANCH_HALT_SKIP,
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.hwcg_reg = 0x80e0,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x80e0,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs1_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs1_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs1c_clk = {
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.halt_reg = 0x8090,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x8090,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs1c_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc video_cc_mvs0c_gdsc = {
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.gdscr = 0x804c,
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.en_rest_wait_val = 0x2,
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.en_few_wait_val = 0x2,
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.clk_dis_wait_val = 0x6,
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.pd = {
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.name = "video_cc_mvs0c_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
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};
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static struct gdsc video_cc_mvs0_gdsc = {
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.gdscr = 0x80a4,
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.en_rest_wait_val = 0x2,
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.en_few_wait_val = 0x2,
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.clk_dis_wait_val = 0x6,
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.pd = {
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.name = "video_cc_mvs0_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.parent = &video_cc_mvs0c_gdsc.pd,
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.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
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};
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static struct gdsc video_cc_mvs1c_gdsc = {
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.gdscr = 0x8078,
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.en_rest_wait_val = 0x2,
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.en_few_wait_val = 0x2,
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.clk_dis_wait_val = 0x6,
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.pd = {
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.name = "video_cc_mvs1c_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
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};
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static struct gdsc video_cc_mvs1_gdsc = {
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.gdscr = 0x80cc,
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.en_rest_wait_val = 0x2,
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.en_few_wait_val = 0x2,
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.clk_dis_wait_val = 0x6,
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.pd = {
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.name = "video_cc_mvs1_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.parent = &video_cc_mvs1c_gdsc.pd,
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.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
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};
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static struct clk_regmap *video_cc_sm8550_clocks[] = {
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[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
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[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
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[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
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[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
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[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
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[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
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[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
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[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
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[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
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[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
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[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
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[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
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};
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static struct gdsc *video_cc_sm8550_gdscs[] = {
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[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
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[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
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[VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
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[VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
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};
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static const struct qcom_reset_map video_cc_sm8550_resets[] = {
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[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
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[CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },
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[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
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[CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
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[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
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[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
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[VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
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};
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static const struct regmap_config video_cc_sm8550_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x9f4c,
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.fast_io = true,
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};
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static struct qcom_cc_desc video_cc_sm8550_desc = {
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.config = &video_cc_sm8550_regmap_config,
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.clks = video_cc_sm8550_clocks,
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.num_clks = ARRAY_SIZE(video_cc_sm8550_clocks),
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.resets = video_cc_sm8550_resets,
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.num_resets = ARRAY_SIZE(video_cc_sm8550_resets),
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.gdscs = video_cc_sm8550_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs),
|
|
};
|
|
|
|
static const struct of_device_id video_cc_sm8550_match_table[] = {
|
|
{ .compatible = "qcom,sm8550-videocc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
|
|
|
|
static int video_cc_sm8550_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
int ret;
|
|
|
|
ret = devm_pm_runtime_enable(&pdev->dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = pm_runtime_resume_and_get(&pdev->dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc);
|
|
if (IS_ERR(regmap)) {
|
|
pm_runtime_put(&pdev->dev);
|
|
return PTR_ERR(regmap);
|
|
}
|
|
|
|
clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
|
|
clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
|
|
|
|
/*
|
|
* Keep clocks always enabled:
|
|
* video_cc_ahb_clk
|
|
* video_cc_sleep_clk
|
|
* video_cc_xo_clk
|
|
*/
|
|
regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0));
|
|
regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0));
|
|
regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
|
|
|
|
ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
|
|
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver video_cc_sm8550_driver = {
|
|
.probe = video_cc_sm8550_probe,
|
|
.driver = {
|
|
.name = "video_cc-sm8550",
|
|
.of_match_table = video_cc_sm8550_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init video_cc_sm8550_init(void)
|
|
{
|
|
return platform_driver_register(&video_cc_sm8550_driver);
|
|
}
|
|
subsys_initcall(video_cc_sm8550_init);
|
|
|
|
static void __exit video_cc_sm8550_exit(void)
|
|
{
|
|
platform_driver_unregister(&video_cc_sm8550_driver);
|
|
}
|
|
module_exit(video_cc_sm8550_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI VIDEOCC SM8550 Driver");
|
|
MODULE_LICENSE("GPL");
|