568 lines
17 KiB
C
568 lines
17 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/printk.h>
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#include <linux/slab.h>
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#include <linux/uaccess.h>
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#include "kfd_priv.h"
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#include "kfd_mqd_manager.h"
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#include "v11_structs.h"
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#include "gc/gc_11_0_0_offset.h"
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#include "gc/gc_11_0_0_sh_mask.h"
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#include "amdgpu_amdkfd.h"
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static inline struct v11_compute_mqd *get_mqd(void *mqd)
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{
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return (struct v11_compute_mqd *)mqd;
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}
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static inline struct v11_sdma_mqd *get_sdma_mqd(void *mqd)
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{
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return (struct v11_sdma_mqd *)mqd;
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}
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static void update_cu_mask(struct mqd_manager *mm, void *mqd,
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struct mqd_update_info *minfo)
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{
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struct v11_compute_mqd *m;
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uint32_t se_mask[KFD_MAX_NUM_SE] = {0};
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bool has_wa_flag = minfo && (minfo->update_flag & (UPDATE_FLAG_DBG_WA_ENABLE |
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UPDATE_FLAG_DBG_WA_DISABLE));
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if (!minfo || !(has_wa_flag || minfo->cu_mask.ptr))
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return;
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m = get_mqd(mqd);
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if (has_wa_flag) {
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uint32_t wa_mask = minfo->update_flag == UPDATE_FLAG_DBG_WA_ENABLE ?
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0xffff : 0xffffffff;
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m->compute_static_thread_mgmt_se0 = wa_mask;
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m->compute_static_thread_mgmt_se1 = wa_mask;
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m->compute_static_thread_mgmt_se2 = wa_mask;
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m->compute_static_thread_mgmt_se3 = wa_mask;
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m->compute_static_thread_mgmt_se4 = wa_mask;
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m->compute_static_thread_mgmt_se5 = wa_mask;
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m->compute_static_thread_mgmt_se6 = wa_mask;
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m->compute_static_thread_mgmt_se7 = wa_mask;
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return;
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}
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mqd_symmetrically_map_cu_mask(mm,
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minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0);
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m->compute_static_thread_mgmt_se0 = se_mask[0];
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m->compute_static_thread_mgmt_se1 = se_mask[1];
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m->compute_static_thread_mgmt_se2 = se_mask[2];
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m->compute_static_thread_mgmt_se3 = se_mask[3];
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m->compute_static_thread_mgmt_se4 = se_mask[4];
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m->compute_static_thread_mgmt_se5 = se_mask[5];
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m->compute_static_thread_mgmt_se6 = se_mask[6];
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m->compute_static_thread_mgmt_se7 = se_mask[7];
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pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n",
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m->compute_static_thread_mgmt_se0,
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m->compute_static_thread_mgmt_se1,
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m->compute_static_thread_mgmt_se2,
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m->compute_static_thread_mgmt_se3,
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m->compute_static_thread_mgmt_se4,
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m->compute_static_thread_mgmt_se5,
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m->compute_static_thread_mgmt_se6,
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m->compute_static_thread_mgmt_se7);
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}
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static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q)
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{
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m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
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m->cp_hqd_queue_priority = q->priority;
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}
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static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
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struct queue_properties *q)
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{
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struct kfd_mem_obj *mqd_mem_obj;
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int size;
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/*
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* MES write to areas beyond MQD size. So allocate
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* 1 PAGE_SIZE memory for MQD is MES is enabled.
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*/
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if (node->kfd->shared_resources.enable_mes)
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size = PAGE_SIZE;
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else
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size = sizeof(struct v11_compute_mqd);
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if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
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return NULL;
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return mqd_mem_obj;
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}
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static void init_mqd(struct mqd_manager *mm, void **mqd,
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struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
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struct queue_properties *q)
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{
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uint64_t addr;
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struct v11_compute_mqd *m;
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int size;
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uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff;
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m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
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addr = mqd_mem_obj->gpu_addr;
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if (mm->dev->kfd->shared_resources.enable_mes)
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size = PAGE_SIZE;
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else
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size = sizeof(struct v11_compute_mqd);
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memset(m, 0, size);
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m->header = 0xC0310800;
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m->compute_pipelinestat_enable = 1;
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m->compute_static_thread_mgmt_se0 = wa_mask;
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m->compute_static_thread_mgmt_se1 = wa_mask;
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m->compute_static_thread_mgmt_se2 = wa_mask;
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m->compute_static_thread_mgmt_se3 = wa_mask;
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m->compute_static_thread_mgmt_se4 = wa_mask;
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m->compute_static_thread_mgmt_se5 = wa_mask;
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m->compute_static_thread_mgmt_se6 = wa_mask;
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m->compute_static_thread_mgmt_se7 = wa_mask;
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m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
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0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
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m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
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m->cp_mqd_base_addr_lo = lower_32_bits(addr);
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m->cp_mqd_base_addr_hi = upper_32_bits(addr);
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m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
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1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
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1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
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/* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the
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* DISPATCH_PTR. This is required for the kfd debugger
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*/
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m->cp_hqd_hq_status0 = 1 << 14;
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/*
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* GFX11 RS64 CPFW version >= 509 supports PCIe atomics support
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* acknowledgment.
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*/
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if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev))
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m->cp_hqd_hq_status0 |= 1 << 29;
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if (q->format == KFD_QUEUE_FORMAT_AQL) {
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m->cp_hqd_aql_control =
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1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
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}
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if (mm->dev->kfd->cwsr_enabled) {
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m->cp_hqd_persistent_state |=
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(1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
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m->cp_hqd_ctx_save_base_addr_lo =
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lower_32_bits(q->ctx_save_restore_area_address);
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m->cp_hqd_ctx_save_base_addr_hi =
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upper_32_bits(q->ctx_save_restore_area_address);
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m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
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m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
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m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
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m->cp_hqd_wg_state_offset = q->ctl_stack_size;
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}
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*mqd = m;
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if (gart_addr)
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*gart_addr = addr;
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mm->update_mqd(mm, m, q, NULL);
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}
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static int load_mqd(struct mqd_manager *mm, void *mqd,
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uint32_t pipe_id, uint32_t queue_id,
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struct queue_properties *p, struct mm_struct *mms)
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{
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int r = 0;
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/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
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uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
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r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id,
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(uint32_t __user *)p->write_ptr,
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wptr_shift, 0, mms, 0);
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return r;
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}
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static void update_mqd(struct mqd_manager *mm, void *mqd,
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struct queue_properties *q,
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struct mqd_update_info *minfo)
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{
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struct v11_compute_mqd *m;
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m = get_mqd(mqd);
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m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
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m->cp_hqd_pq_control |=
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ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
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pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
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m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
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m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
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m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
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m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
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m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
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m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
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m->cp_hqd_pq_doorbell_control =
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q->doorbell_off <<
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CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
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pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
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m->cp_hqd_pq_doorbell_control);
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m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT;
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/*
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* HW does not clamp this field correctly. Maximum EOP queue size
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* is constrained by per-SE EOP done signal count, which is 8-bit.
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* Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
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* more than (EOP entry count - 1) so a queue size of 0x800 dwords
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* is safe, giving a maximum field value of 0xA.
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*/
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m->cp_hqd_eop_control = min(0xA,
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ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);
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m->cp_hqd_eop_base_addr_lo =
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lower_32_bits(q->eop_ring_buffer_address >> 8);
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m->cp_hqd_eop_base_addr_hi =
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upper_32_bits(q->eop_ring_buffer_address >> 8);
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m->cp_hqd_iq_timer = 0;
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m->cp_hqd_vmid = q->vmid;
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if (q->format == KFD_QUEUE_FORMAT_AQL) {
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/* GC 10 removed WPP_CLAMP from PQ Control */
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m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
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2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |
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1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT ;
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m->cp_hqd_pq_doorbell_control |=
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1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;
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}
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if (mm->dev->kfd->cwsr_enabled)
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m->cp_hqd_ctx_save_control = 0;
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update_cu_mask(mm, mqd, minfo);
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set_priority(m, q);
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q->is_active = QUEUE_IS_ACTIVE(*q);
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}
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static uint32_t read_doorbell_id(void *mqd)
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{
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struct v11_compute_mqd *m = (struct v11_compute_mqd *)mqd;
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return m->queue_doorbell_id0;
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}
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static int get_wave_state(struct mqd_manager *mm, void *mqd,
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struct queue_properties *q,
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void __user *ctl_stack,
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u32 *ctl_stack_used_size,
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u32 *save_area_used_size)
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{
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struct v11_compute_mqd *m;
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struct kfd_context_save_area_header header;
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m = get_mqd(mqd);
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/* Control stack is written backwards, while workgroup context data
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* is written forwards. Both starts from m->cp_hqd_cntl_stack_size.
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* Current position is at m->cp_hqd_cntl_stack_offset and
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* m->cp_hqd_wg_state_offset, respectively.
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*/
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*ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
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m->cp_hqd_cntl_stack_offset;
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*save_area_used_size = m->cp_hqd_wg_state_offset -
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m->cp_hqd_cntl_stack_size;
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/* Control stack is not copied to user mode for GFXv11 because
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* it's part of the context save area that is already
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* accessible to user mode
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*/
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header.wave_state.control_stack_size = *ctl_stack_used_size;
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header.wave_state.wave_state_size = *save_area_used_size;
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header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset;
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header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset;
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if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state)))
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return -EFAULT;
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return 0;
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}
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static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst)
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{
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struct v11_compute_mqd *m;
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m = get_mqd(mqd);
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memcpy(mqd_dst, m, sizeof(struct v11_compute_mqd));
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}
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static void restore_mqd(struct mqd_manager *mm, void **mqd,
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struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
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struct queue_properties *qp,
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const void *mqd_src,
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const void *ctl_stack_src, const u32 ctl_stack_size)
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{
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uint64_t addr;
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struct v11_compute_mqd *m;
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m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
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addr = mqd_mem_obj->gpu_addr;
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memcpy(m, mqd_src, sizeof(*m));
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*mqd = m;
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if (gart_addr)
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*gart_addr = addr;
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m->cp_hqd_pq_doorbell_control =
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qp->doorbell_off <<
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CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
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pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
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m->cp_hqd_pq_doorbell_control);
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qp->is_active = 0;
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}
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static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
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struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
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struct queue_properties *q)
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{
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struct v11_compute_mqd *m;
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init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
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m = get_mqd(*mqd);
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m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
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1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
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}
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static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd,
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enum kfd_preempt_type type, unsigned int timeout,
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uint32_t pipe_id, uint32_t queue_id)
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{
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int err;
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struct v11_compute_mqd *m;
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u32 doorbell_off;
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m = get_mqd(mqd);
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doorbell_off = m->cp_hqd_pq_doorbell_control >>
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CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
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err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0);
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if (err)
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pr_debug("Destroy HIQ MQD failed: %d\n", err);
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return err;
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}
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static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
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struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
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struct queue_properties *q)
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{
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struct v11_sdma_mqd *m;
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int size;
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m = (struct v11_sdma_mqd *) mqd_mem_obj->cpu_ptr;
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if (mm->dev->kfd->shared_resources.enable_mes)
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size = PAGE_SIZE;
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else
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size = sizeof(struct v11_sdma_mqd);
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memset(m, 0, size);
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*mqd = m;
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if (gart_addr)
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*gart_addr = mqd_mem_obj->gpu_addr;
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mm->update_mqd(mm, m, q, NULL);
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}
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#define SDMA_RLC_DUMMY_DEFAULT 0xf
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static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
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struct queue_properties *q,
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struct mqd_update_info *minfo)
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{
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struct v11_sdma_mqd *m;
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m = get_sdma_mqd(mqd);
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m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
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<< SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
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q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT |
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1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
|
|
6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
|
|
1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
|
|
|
|
m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
|
|
m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
|
|
m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
|
|
m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
|
|
m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
|
|
m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
|
|
m->sdmax_rlcx_doorbell_offset =
|
|
q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
|
|
|
|
m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum
|
|
<< SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT)
|
|
& SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK;
|
|
|
|
m->sdma_engine_id = q->sdma_engine_id;
|
|
m->sdma_queue_id = q->sdma_queue_id;
|
|
m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
|
|
|
|
q->is_active = QUEUE_IS_ACTIVE(*q);
|
|
}
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int debugfs_show_mqd(struct seq_file *m, void *data)
|
|
{
|
|
seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
|
|
data, sizeof(struct v11_compute_mqd), false);
|
|
return 0;
|
|
}
|
|
|
|
static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
|
|
{
|
|
seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
|
|
data, sizeof(struct v11_sdma_mqd), false);
|
|
return 0;
|
|
}
|
|
|
|
#endif
|
|
|
|
struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type,
|
|
struct kfd_node *dev)
|
|
{
|
|
struct mqd_manager *mqd;
|
|
|
|
if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
|
|
return NULL;
|
|
|
|
mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
|
|
if (!mqd)
|
|
return NULL;
|
|
|
|
mqd->dev = dev;
|
|
|
|
switch (type) {
|
|
case KFD_MQD_TYPE_CP:
|
|
pr_debug("%s@%i\n", __func__, __LINE__);
|
|
mqd->allocate_mqd = allocate_mqd;
|
|
mqd->init_mqd = init_mqd;
|
|
mqd->free_mqd = kfd_free_mqd_cp;
|
|
mqd->load_mqd = load_mqd;
|
|
mqd->update_mqd = update_mqd;
|
|
mqd->destroy_mqd = kfd_destroy_mqd_cp;
|
|
mqd->is_occupied = kfd_is_occupied_cp;
|
|
mqd->mqd_size = sizeof(struct v11_compute_mqd);
|
|
mqd->get_wave_state = get_wave_state;
|
|
mqd->mqd_stride = kfd_mqd_stride;
|
|
mqd->checkpoint_mqd = checkpoint_mqd;
|
|
mqd->restore_mqd = restore_mqd;
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
mqd->debugfs_show_mqd = debugfs_show_mqd;
|
|
#endif
|
|
pr_debug("%s@%i\n", __func__, __LINE__);
|
|
break;
|
|
case KFD_MQD_TYPE_HIQ:
|
|
pr_debug("%s@%i\n", __func__, __LINE__);
|
|
mqd->allocate_mqd = allocate_hiq_mqd;
|
|
mqd->init_mqd = init_mqd_hiq;
|
|
mqd->free_mqd = free_mqd_hiq_sdma;
|
|
mqd->load_mqd = kfd_hiq_load_mqd_kiq;
|
|
mqd->update_mqd = update_mqd;
|
|
mqd->destroy_mqd = destroy_hiq_mqd;
|
|
mqd->is_occupied = kfd_is_occupied_cp;
|
|
mqd->mqd_size = sizeof(struct v11_compute_mqd);
|
|
mqd->mqd_stride = kfd_mqd_stride;
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
mqd->debugfs_show_mqd = debugfs_show_mqd;
|
|
#endif
|
|
mqd->read_doorbell_id = read_doorbell_id;
|
|
pr_debug("%s@%i\n", __func__, __LINE__);
|
|
break;
|
|
case KFD_MQD_TYPE_DIQ:
|
|
mqd->allocate_mqd = allocate_mqd;
|
|
mqd->init_mqd = init_mqd_hiq;
|
|
mqd->free_mqd = kfd_free_mqd_cp;
|
|
mqd->load_mqd = load_mqd;
|
|
mqd->update_mqd = update_mqd;
|
|
mqd->destroy_mqd = kfd_destroy_mqd_cp;
|
|
mqd->is_occupied = kfd_is_occupied_cp;
|
|
mqd->mqd_size = sizeof(struct v11_compute_mqd);
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
mqd->debugfs_show_mqd = debugfs_show_mqd;
|
|
#endif
|
|
break;
|
|
case KFD_MQD_TYPE_SDMA:
|
|
pr_debug("%s@%i\n", __func__, __LINE__);
|
|
mqd->allocate_mqd = allocate_sdma_mqd;
|
|
mqd->init_mqd = init_mqd_sdma;
|
|
mqd->free_mqd = free_mqd_hiq_sdma;
|
|
mqd->load_mqd = kfd_load_mqd_sdma;
|
|
mqd->update_mqd = update_mqd_sdma;
|
|
mqd->destroy_mqd = kfd_destroy_mqd_sdma;
|
|
mqd->is_occupied = kfd_is_occupied_sdma;
|
|
mqd->checkpoint_mqd = checkpoint_mqd;
|
|
mqd->restore_mqd = restore_mqd;
|
|
mqd->mqd_size = sizeof(struct v11_sdma_mqd);
|
|
mqd->mqd_stride = kfd_mqd_stride;
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
|
|
#endif
|
|
/*
|
|
* To allocate SDMA MQDs by generic functions
|
|
* when MES is enabled.
|
|
*/
|
|
if (dev->kfd->shared_resources.enable_mes) {
|
|
mqd->allocate_mqd = allocate_mqd;
|
|
mqd->free_mqd = kfd_free_mqd_cp;
|
|
}
|
|
pr_debug("%s@%i\n", __func__, __LINE__);
|
|
break;
|
|
default:
|
|
kfree(mqd);
|
|
return NULL;
|
|
}
|
|
|
|
return mqd;
|
|
}
|