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![Jonathan Cameron](/assets/img/avatar_default.png)
Fixes tag is where the max channels became 8, but timestamp space was missing
before that.
Fixes: 851644a60d
("iio: adc: ad7923: Add support for the ad7908/ad7918/ad7928")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Daniel Junho <djunho@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20210501165314.511954-3-jic23@kernel.org
Cc: <Stable@vger.kernel.org>
393 lines
9.9 KiB
C
393 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AD7904/AD7914/AD7923/AD7924/AD7908/AD7918/AD7928 SPI ADC driver
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*
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* Copyright 2011 Analog Devices Inc (from AD7923 Driver)
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* Copyright 2012 CS Systemes d'Information
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/sysfs.h>
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#include <linux/spi/spi.h>
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#include <linux/regulator/consumer.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#define AD7923_WRITE_CR BIT(11) /* write control register */
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#define AD7923_RANGE BIT(1) /* range to REFin */
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#define AD7923_CODING BIT(0) /* coding is straight binary */
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#define AD7923_PM_MODE_AS (1) /* auto shutdown */
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#define AD7923_PM_MODE_FS (2) /* full shutdown */
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#define AD7923_PM_MODE_OPS (3) /* normal operation */
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#define AD7923_SEQUENCE_OFF (0) /* no sequence fonction */
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#define AD7923_SEQUENCE_PROTECT (2) /* no interrupt write cycle */
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#define AD7923_SEQUENCE_ON (3) /* continuous sequence */
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#define AD7923_PM_MODE_WRITE(mode) ((mode) << 4) /* write mode */
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#define AD7923_CHANNEL_WRITE(channel) ((channel) << 6) /* write channel */
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#define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \
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+ (((sequence) & 2) << 9))
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/* write sequence fonction */
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/* left shift for CR : bit 11 transmit in first */
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#define AD7923_SHIFT_REGISTER 4
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/* val = value, dec = left shift, bits = number of bits of the mask */
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#define EXTRACT(val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1))
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struct ad7923_state {
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struct spi_device *spi;
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struct spi_transfer ring_xfer[5];
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struct spi_transfer scan_single_xfer[2];
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struct spi_message ring_msg;
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struct spi_message scan_single_msg;
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struct regulator *reg;
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unsigned int settings;
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/*
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* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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* Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp
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* Length = 8 channels + 4 extra for 8 byte timestamp
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*/
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__be16 rx_buf[12] ____cacheline_aligned;
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__be16 tx_buf[4];
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};
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struct ad7923_chip_info {
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const struct iio_chan_spec *channels;
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unsigned int num_channels;
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};
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enum ad7923_id {
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AD7904,
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AD7914,
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AD7924,
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AD7908,
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AD7918,
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AD7928
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};
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#define AD7923_V_CHAN(index, bits) \
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{ \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = index, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.address = index, \
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.scan_index = index, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = (bits), \
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.storagebits = 16, \
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.endianness = IIO_BE, \
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}, \
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}
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#define DECLARE_AD7923_CHANNELS(name, bits) \
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const struct iio_chan_spec name ## _channels[] = { \
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AD7923_V_CHAN(0, bits), \
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AD7923_V_CHAN(1, bits), \
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AD7923_V_CHAN(2, bits), \
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AD7923_V_CHAN(3, bits), \
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IIO_CHAN_SOFT_TIMESTAMP(4), \
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}
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#define DECLARE_AD7908_CHANNELS(name, bits) \
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const struct iio_chan_spec name ## _channels[] = { \
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AD7923_V_CHAN(0, bits), \
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AD7923_V_CHAN(1, bits), \
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AD7923_V_CHAN(2, bits), \
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AD7923_V_CHAN(3, bits), \
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AD7923_V_CHAN(4, bits), \
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AD7923_V_CHAN(5, bits), \
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AD7923_V_CHAN(6, bits), \
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AD7923_V_CHAN(7, bits), \
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IIO_CHAN_SOFT_TIMESTAMP(8), \
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}
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static DECLARE_AD7923_CHANNELS(ad7904, 8);
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static DECLARE_AD7923_CHANNELS(ad7914, 10);
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static DECLARE_AD7923_CHANNELS(ad7924, 12);
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static DECLARE_AD7908_CHANNELS(ad7908, 8);
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static DECLARE_AD7908_CHANNELS(ad7918, 10);
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static DECLARE_AD7908_CHANNELS(ad7928, 12);
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static const struct ad7923_chip_info ad7923_chip_info[] = {
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[AD7904] = {
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.channels = ad7904_channels,
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.num_channels = ARRAY_SIZE(ad7904_channels),
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},
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[AD7914] = {
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.channels = ad7914_channels,
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.num_channels = ARRAY_SIZE(ad7914_channels),
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},
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[AD7924] = {
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.channels = ad7924_channels,
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.num_channels = ARRAY_SIZE(ad7924_channels),
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},
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[AD7908] = {
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.channels = ad7908_channels,
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.num_channels = ARRAY_SIZE(ad7908_channels),
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},
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[AD7918] = {
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.channels = ad7918_channels,
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.num_channels = ARRAY_SIZE(ad7918_channels),
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},
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[AD7928] = {
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.channels = ad7928_channels,
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.num_channels = ARRAY_SIZE(ad7928_channels),
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},
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};
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/*
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* ad7923_update_scan_mode() setup the spi transfer buffer for the new scan mask
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*/
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static int ad7923_update_scan_mode(struct iio_dev *indio_dev,
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const unsigned long *active_scan_mask)
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{
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struct ad7923_state *st = iio_priv(indio_dev);
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int i, cmd, len;
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len = 0;
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/*
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* For this driver the last channel is always the software timestamp so
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* skip that one.
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*/
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for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) {
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cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(i) |
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AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
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st->settings;
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cmd <<= AD7923_SHIFT_REGISTER;
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st->tx_buf[len++] = cpu_to_be16(cmd);
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}
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/* build spi ring message */
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st->ring_xfer[0].tx_buf = &st->tx_buf[0];
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st->ring_xfer[0].len = len;
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st->ring_xfer[0].cs_change = 1;
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spi_message_init(&st->ring_msg);
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spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
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for (i = 0; i < len; i++) {
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st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i];
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st->ring_xfer[i + 1].len = 2;
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st->ring_xfer[i + 1].cs_change = 1;
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spi_message_add_tail(&st->ring_xfer[i + 1], &st->ring_msg);
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}
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/* make sure last transfer cs_change is not set */
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st->ring_xfer[i + 1].cs_change = 0;
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return 0;
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}
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static irqreturn_t ad7923_trigger_handler(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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struct iio_dev *indio_dev = pf->indio_dev;
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struct ad7923_state *st = iio_priv(indio_dev);
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int b_sent;
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b_sent = spi_sync(st->spi, &st->ring_msg);
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if (b_sent)
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goto done;
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iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
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iio_get_time_ns(indio_dev));
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done:
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iio_trigger_notify_done(indio_dev->trig);
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return IRQ_HANDLED;
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}
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static int ad7923_scan_direct(struct ad7923_state *st, unsigned int ch)
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{
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int ret, cmd;
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cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(ch) |
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AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
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st->settings;
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cmd <<= AD7923_SHIFT_REGISTER;
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st->tx_buf[0] = cpu_to_be16(cmd);
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ret = spi_sync(st->spi, &st->scan_single_msg);
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if (ret)
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return ret;
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return be16_to_cpu(st->rx_buf[0]);
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}
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static int ad7923_get_range(struct ad7923_state *st)
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{
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int vref;
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vref = regulator_get_voltage(st->reg);
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if (vref < 0)
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return vref;
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vref /= 1000;
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if (!(st->settings & AD7923_RANGE))
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vref *= 2;
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return vref;
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}
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static int ad7923_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long m)
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{
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int ret;
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struct ad7923_state *st = iio_priv(indio_dev);
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switch (m) {
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case IIO_CHAN_INFO_RAW:
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ret = iio_device_claim_direct_mode(indio_dev);
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if (ret)
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return ret;
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ret = ad7923_scan_direct(st, chan->address);
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iio_device_release_direct_mode(indio_dev);
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if (ret < 0)
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return ret;
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if (chan->address == EXTRACT(ret, 12, 4))
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*val = EXTRACT(ret, 0, 12);
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else
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return -EIO;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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ret = ad7923_get_range(st);
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if (ret < 0)
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return ret;
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*val = ret;
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*val2 = chan->scan_type.realbits;
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return IIO_VAL_FRACTIONAL_LOG2;
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}
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return -EINVAL;
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}
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static const struct iio_info ad7923_info = {
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.read_raw = &ad7923_read_raw,
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.update_scan_mode = ad7923_update_scan_mode,
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};
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static void ad7923_regulator_disable(void *data)
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{
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struct ad7923_state *st = data;
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regulator_disable(st->reg);
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}
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static int ad7923_probe(struct spi_device *spi)
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{
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struct ad7923_state *st;
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struct iio_dev *indio_dev;
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const struct ad7923_chip_info *info;
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int ret;
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indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
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if (!indio_dev)
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return -ENOMEM;
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st = iio_priv(indio_dev);
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st->spi = spi;
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st->settings = AD7923_CODING | AD7923_RANGE |
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AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS);
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info = &ad7923_chip_info[spi_get_device_id(spi)->driver_data];
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indio_dev->name = spi_get_device_id(spi)->name;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = info->channels;
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indio_dev->num_channels = info->num_channels;
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indio_dev->info = &ad7923_info;
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/* Setup default message */
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st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
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st->scan_single_xfer[0].len = 2;
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st->scan_single_xfer[0].cs_change = 1;
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st->scan_single_xfer[1].rx_buf = &st->rx_buf[0];
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st->scan_single_xfer[1].len = 2;
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spi_message_init(&st->scan_single_msg);
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spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
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spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
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st->reg = devm_regulator_get(&spi->dev, "refin");
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if (IS_ERR(st->reg))
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return PTR_ERR(st->reg);
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ret = regulator_enable(st->reg);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(&spi->dev, ad7923_regulator_disable, st);
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if (ret)
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return ret;
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ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
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&ad7923_trigger_handler, NULL);
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if (ret)
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return ret;
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return devm_iio_device_register(&spi->dev, indio_dev);
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}
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static const struct spi_device_id ad7923_id[] = {
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{"ad7904", AD7904},
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{"ad7914", AD7914},
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{"ad7923", AD7924},
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{"ad7924", AD7924},
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{"ad7908", AD7908},
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{"ad7918", AD7918},
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{"ad7928", AD7928},
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{}
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};
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MODULE_DEVICE_TABLE(spi, ad7923_id);
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static const struct of_device_id ad7923_of_match[] = {
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{ .compatible = "adi,ad7904", },
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{ .compatible = "adi,ad7914", },
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{ .compatible = "adi,ad7923", },
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{ .compatible = "adi,ad7924", },
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{ .compatible = "adi,ad7908", },
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{ .compatible = "adi,ad7918", },
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{ .compatible = "adi,ad7928", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ad7923_of_match);
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static struct spi_driver ad7923_driver = {
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.driver = {
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.name = "ad7923",
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.of_match_table = ad7923_of_match,
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},
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.probe = ad7923_probe,
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.id_table = ad7923_id,
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};
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module_spi_driver(ad7923_driver);
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MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
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MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>");
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MODULE_DESCRIPTION("Analog Devices AD7923 and similar ADC");
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MODULE_LICENSE("GPL v2");
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