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![Jonathan Cameron](/assets/img/avatar_default.png)
Whilst is unlikely anyone will be using this part with an ACPI PRP0001 based binding any time soon, we are getting a lot of cut and pasting of this pattern so I am looking to remove it entirely from IIO. In this case CONFIG_OF protections also removed and mod_devicetable.h include added given direct use of struct of_device_id. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
231 lines
5.6 KiB
C
231 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* lpc32xx_adc.c - Support for ADC in LPC32XX
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*
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* 3-channel, 10-bit ADC
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*
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* Copyright (C) 2011, 2012 Roland Stigge <stigge@antcom.de>
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/err.h>
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#include <linux/iio/iio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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/*
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* LPC32XX registers definitions
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*/
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#define LPC32XXAD_SELECT(x) ((x) + 0x04)
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#define LPC32XXAD_CTRL(x) ((x) + 0x08)
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#define LPC32XXAD_VALUE(x) ((x) + 0x48)
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/* Bit definitions for LPC32XXAD_SELECT: */
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/* constant, always write this value! */
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#define LPC32XXAD_REFm 0x00000200
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/* constant, always write this value! */
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#define LPC32XXAD_REFp 0x00000080
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/* multiple of this is the channel number: 0, 1, 2 */
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#define LPC32XXAD_IN 0x00000010
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/* constant, always write this value! */
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#define LPC32XXAD_INTERNAL 0x00000004
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/* Bit definitions for LPC32XXAD_CTRL: */
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#define LPC32XXAD_STROBE 0x00000002
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#define LPC32XXAD_PDN_CTRL 0x00000004
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/* Bit definitions for LPC32XXAD_VALUE: */
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#define LPC32XXAD_VALUE_MASK 0x000003FF
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#define LPC32XXAD_NAME "lpc32xx-adc"
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struct lpc32xx_adc_state {
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void __iomem *adc_base;
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struct clk *clk;
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struct completion completion;
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struct regulator *vref;
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u32 value;
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};
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static int lpc32xx_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long mask)
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{
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struct lpc32xx_adc_state *st = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&indio_dev->mlock);
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ret = clk_prepare_enable(st->clk);
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if (ret) {
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mutex_unlock(&indio_dev->mlock);
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return ret;
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}
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/* Measurement setup */
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__raw_writel(LPC32XXAD_INTERNAL | (chan->address) |
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LPC32XXAD_REFp | LPC32XXAD_REFm,
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LPC32XXAD_SELECT(st->adc_base));
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/* Trigger conversion */
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__raw_writel(LPC32XXAD_PDN_CTRL | LPC32XXAD_STROBE,
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LPC32XXAD_CTRL(st->adc_base));
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wait_for_completion(&st->completion); /* set by ISR */
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clk_disable_unprepare(st->clk);
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*val = st->value;
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mutex_unlock(&indio_dev->mlock);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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*val = regulator_get_voltage(st->vref) / 1000;
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*val2 = 10;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
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static const struct iio_info lpc32xx_adc_iio_info = {
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.read_raw = &lpc32xx_read_raw,
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};
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#define LPC32XX_ADC_CHANNEL_BASE(_index) \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = _index, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.address = LPC32XXAD_IN * _index, \
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.scan_index = _index,
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#define LPC32XX_ADC_CHANNEL(_index) { \
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LPC32XX_ADC_CHANNEL_BASE(_index) \
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}
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#define LPC32XX_ADC_SCALE_CHANNEL(_index) { \
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LPC32XX_ADC_CHANNEL_BASE(_index) \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
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}
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static const struct iio_chan_spec lpc32xx_adc_iio_channels[] = {
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LPC32XX_ADC_CHANNEL(0),
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LPC32XX_ADC_CHANNEL(1),
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LPC32XX_ADC_CHANNEL(2),
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};
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static const struct iio_chan_spec lpc32xx_adc_iio_scale_channels[] = {
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LPC32XX_ADC_SCALE_CHANNEL(0),
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LPC32XX_ADC_SCALE_CHANNEL(1),
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LPC32XX_ADC_SCALE_CHANNEL(2),
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};
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static irqreturn_t lpc32xx_adc_isr(int irq, void *dev_id)
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{
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struct lpc32xx_adc_state *st = dev_id;
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/* Read value and clear irq */
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st->value = __raw_readl(LPC32XXAD_VALUE(st->adc_base)) &
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LPC32XXAD_VALUE_MASK;
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complete(&st->completion);
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return IRQ_HANDLED;
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}
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static int lpc32xx_adc_probe(struct platform_device *pdev)
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{
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struct lpc32xx_adc_state *st = NULL;
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struct resource *res;
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int retval = -ENODEV;
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struct iio_dev *iodev = NULL;
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int irq;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "failed to get platform I/O memory\n");
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return -ENXIO;
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}
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iodev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
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if (!iodev)
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return -ENOMEM;
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st = iio_priv(iodev);
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st->adc_base = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!st->adc_base) {
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dev_err(&pdev->dev, "failed mapping memory\n");
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return -EBUSY;
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}
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st->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(st->clk)) {
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dev_err(&pdev->dev, "failed getting clock\n");
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return PTR_ERR(st->clk);
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}
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0)
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return -ENXIO;
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retval = devm_request_irq(&pdev->dev, irq, lpc32xx_adc_isr, 0,
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LPC32XXAD_NAME, st);
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if (retval < 0) {
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dev_err(&pdev->dev, "failed requesting interrupt\n");
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return retval;
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}
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st->vref = devm_regulator_get(&pdev->dev, "vref");
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if (IS_ERR(st->vref)) {
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iodev->channels = lpc32xx_adc_iio_channels;
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dev_info(&pdev->dev,
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"Missing vref regulator: No scaling available\n");
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} else {
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iodev->channels = lpc32xx_adc_iio_scale_channels;
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}
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platform_set_drvdata(pdev, iodev);
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init_completion(&st->completion);
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iodev->name = LPC32XXAD_NAME;
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iodev->info = &lpc32xx_adc_iio_info;
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iodev->modes = INDIO_DIRECT_MODE;
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iodev->num_channels = ARRAY_SIZE(lpc32xx_adc_iio_channels);
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retval = devm_iio_device_register(&pdev->dev, iodev);
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if (retval)
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return retval;
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dev_info(&pdev->dev, "LPC32XX ADC driver loaded, IRQ %d\n", irq);
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return 0;
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}
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static const struct of_device_id lpc32xx_adc_match[] = {
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{ .compatible = "nxp,lpc3220-adc" },
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{},
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};
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MODULE_DEVICE_TABLE(of, lpc32xx_adc_match);
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static struct platform_driver lpc32xx_adc_driver = {
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.probe = lpc32xx_adc_probe,
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.driver = {
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.name = LPC32XXAD_NAME,
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.of_match_table = lpc32xx_adc_match,
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},
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};
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module_platform_driver(lpc32xx_adc_driver);
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MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
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MODULE_DESCRIPTION("LPC32XX ADC driver");
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MODULE_LICENSE("GPL");
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