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![Jonathan Cameron](/assets/img/avatar_default.png)
Already set to the same value in devm_iio_device_alloc() Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Gene Chen <gene_chen@richtek.com> Reviewed-by: Alexandru Ardelean <ardeleanalex@gmail.com> Link: https://lore.kernel.org/r/20210426170251.351957-5-jic23@kernel.org
372 lines
9.9 KiB
C
372 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/bits.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/ktime.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <asm/unaligned.h>
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#define MT6360_REG_PMUCHGCTRL3 0x313
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#define MT6360_REG_PMUADCCFG 0x356
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#define MT6360_REG_PMUADCIDLET 0x358
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#define MT6360_REG_PMUADCRPT1 0x35A
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/* PMUCHGCTRL3 0x313 */
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#define MT6360_AICR_MASK GENMASK(7, 2)
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#define MT6360_AICR_SHFT 2
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#define MT6360_AICR_400MA 0x6
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/* PMUADCCFG 0x356 */
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#define MT6360_ADCEN_MASK BIT(15)
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/* PMUADCRPT1 0x35A */
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#define MT6360_PREFERCH_MASK GENMASK(7, 4)
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#define MT6360_PREFERCH_SHFT 4
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#define MT6360_RPTCH_MASK GENMASK(3, 0)
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#define MT6360_NO_PREFER 15
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/* Time in ms */
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#define ADC_WAIT_TIME_MS 25
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#define ADC_CONV_TIMEOUT_MS 100
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#define ADC_LOOP_TIME_US 2000
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enum {
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MT6360_CHAN_USBID = 0,
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MT6360_CHAN_VBUSDIV5,
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MT6360_CHAN_VBUSDIV2,
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MT6360_CHAN_VSYS,
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MT6360_CHAN_VBAT,
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MT6360_CHAN_IBUS,
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MT6360_CHAN_IBAT,
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MT6360_CHAN_CHG_VDDP,
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MT6360_CHAN_TEMP_JC,
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MT6360_CHAN_VREF_TS,
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MT6360_CHAN_TS,
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MT6360_CHAN_MAX
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};
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struct mt6360_adc_data {
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struct device *dev;
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struct regmap *regmap;
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/* Due to only one set of ADC control, this lock is used to prevent the race condition */
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struct mutex adc_lock;
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ktime_t last_off_timestamps[MT6360_CHAN_MAX];
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};
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static int mt6360_adc_read_channel(struct mt6360_adc_data *mad, int channel, int *val)
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{
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__be16 adc_enable;
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u8 rpt[3];
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ktime_t predict_end_t, timeout;
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unsigned int pre_wait_time;
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int ret;
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mutex_lock(&mad->adc_lock);
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/* Select the preferred ADC channel */
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ret = regmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK,
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channel << MT6360_PREFERCH_SHFT);
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if (ret)
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goto out_adc_lock;
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adc_enable = cpu_to_be16(MT6360_ADCEN_MASK | BIT(channel));
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ret = regmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable));
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if (ret)
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goto out_adc_lock;
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predict_end_t = ktime_add_ms(mad->last_off_timestamps[channel], 2 * ADC_WAIT_TIME_MS);
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if (ktime_after(ktime_get(), predict_end_t))
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pre_wait_time = ADC_WAIT_TIME_MS;
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else
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pre_wait_time = 3 * ADC_WAIT_TIME_MS;
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if (msleep_interruptible(pre_wait_time)) {
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ret = -ERESTARTSYS;
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goto out_adc_conv;
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}
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timeout = ktime_add_ms(ktime_get(), ADC_CONV_TIMEOUT_MS);
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while (true) {
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ret = regmap_raw_read(mad->regmap, MT6360_REG_PMUADCRPT1, rpt, sizeof(rpt));
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if (ret)
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goto out_adc_conv;
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/*
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* There are two functions, ZCV and TypeC OTP, running ADC VBAT and TS in
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* background, and ADC samples are taken on a fixed frequency no matter read the
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* previous one or not.
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* To avoid conflict, We set minimum time threshold after enable ADC and
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* check report channel is the same.
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* The worst case is run the same ADC twice and background function is also running,
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* ADC conversion sequence is desire channel before start ADC, background ADC,
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* desire channel after start ADC.
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* So the minimum correct data is three times of typical conversion time.
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*/
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if ((rpt[0] & MT6360_RPTCH_MASK) == channel)
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break;
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if (ktime_compare(ktime_get(), timeout) > 0) {
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ret = -ETIMEDOUT;
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goto out_adc_conv;
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}
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usleep_range(ADC_LOOP_TIME_US / 2, ADC_LOOP_TIME_US);
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}
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*val = rpt[1] << 8 | rpt[2];
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ret = IIO_VAL_INT;
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out_adc_conv:
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/* Only keep ADC enable */
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adc_enable = cpu_to_be16(MT6360_ADCEN_MASK);
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regmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable));
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mad->last_off_timestamps[channel] = ktime_get();
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/* Config prefer channel to NO_PREFER */
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regmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK,
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MT6360_NO_PREFER << MT6360_PREFERCH_SHFT);
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out_adc_lock:
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mutex_unlock(&mad->adc_lock);
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return ret;
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}
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static int mt6360_adc_read_scale(struct mt6360_adc_data *mad, int channel, int *val, int *val2)
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{
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unsigned int regval;
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int ret;
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switch (channel) {
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case MT6360_CHAN_USBID:
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case MT6360_CHAN_VSYS:
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case MT6360_CHAN_VBAT:
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case MT6360_CHAN_CHG_VDDP:
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case MT6360_CHAN_VREF_TS:
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case MT6360_CHAN_TS:
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*val = 1250;
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return IIO_VAL_INT;
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case MT6360_CHAN_VBUSDIV5:
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*val = 6250;
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return IIO_VAL_INT;
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case MT6360_CHAN_VBUSDIV2:
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case MT6360_CHAN_IBUS:
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case MT6360_CHAN_IBAT:
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*val = 2500;
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if (channel == MT6360_CHAN_IBUS) {
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/* IBUS will be affected by input current limit for the different Ron */
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/* Check whether the config is <400mA or not */
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ret = regmap_read(mad->regmap, MT6360_REG_PMUCHGCTRL3, ®val);
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if (ret)
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return ret;
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regval = (regval & MT6360_AICR_MASK) >> MT6360_AICR_SHFT;
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if (regval < MT6360_AICR_400MA)
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*val = 1900;
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}
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return IIO_VAL_INT;
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case MT6360_CHAN_TEMP_JC:
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*val = 105;
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*val2 = 100;
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return IIO_VAL_FRACTIONAL;
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}
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return -EINVAL;
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}
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static int mt6360_adc_read_offset(struct mt6360_adc_data *mad, int channel, int *val)
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{
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*val = (channel == MT6360_CHAN_TEMP_JC) ? -80 : 0;
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return IIO_VAL_INT;
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}
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static int mt6360_adc_read_raw(struct iio_dev *iio_dev, const struct iio_chan_spec *chan,
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int *val, int *val2, long mask)
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{
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struct mt6360_adc_data *mad = iio_priv(iio_dev);
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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return mt6360_adc_read_channel(mad, chan->channel, val);
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case IIO_CHAN_INFO_SCALE:
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return mt6360_adc_read_scale(mad, chan->channel, val, val2);
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case IIO_CHAN_INFO_OFFSET:
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return mt6360_adc_read_offset(mad, chan->channel, val);
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}
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return -EINVAL;
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}
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static const char *mt6360_channel_labels[MT6360_CHAN_MAX] = {
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"usbid", "vbusdiv5", "vbusdiv2", "vsys", "vbat", "ibus", "ibat", "chg_vddp",
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"temp_jc", "vref_ts", "ts",
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};
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static int mt6360_adc_read_label(struct iio_dev *iio_dev, const struct iio_chan_spec *chan,
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char *label)
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{
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return snprintf(label, PAGE_SIZE, "%s\n", mt6360_channel_labels[chan->channel]);
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}
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static const struct iio_info mt6360_adc_iio_info = {
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.read_raw = mt6360_adc_read_raw,
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.read_label = mt6360_adc_read_label,
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};
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#define MT6360_ADC_CHAN(_idx, _type) { \
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.type = _type, \
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.channel = MT6360_CHAN_##_idx, \
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.scan_index = MT6360_CHAN_##_idx, \
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.datasheet_name = #_idx, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = 16, \
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.storagebits = 16, \
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.endianness = IIO_CPU, \
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}, \
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.indexed = 1, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_OFFSET), \
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}
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static const struct iio_chan_spec mt6360_adc_channels[] = {
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MT6360_ADC_CHAN(USBID, IIO_VOLTAGE),
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MT6360_ADC_CHAN(VBUSDIV5, IIO_VOLTAGE),
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MT6360_ADC_CHAN(VBUSDIV2, IIO_VOLTAGE),
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MT6360_ADC_CHAN(VSYS, IIO_VOLTAGE),
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MT6360_ADC_CHAN(VBAT, IIO_VOLTAGE),
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MT6360_ADC_CHAN(IBUS, IIO_CURRENT),
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MT6360_ADC_CHAN(IBAT, IIO_CURRENT),
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MT6360_ADC_CHAN(CHG_VDDP, IIO_VOLTAGE),
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MT6360_ADC_CHAN(TEMP_JC, IIO_TEMP),
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MT6360_ADC_CHAN(VREF_TS, IIO_VOLTAGE),
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MT6360_ADC_CHAN(TS, IIO_VOLTAGE),
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IIO_CHAN_SOFT_TIMESTAMP(MT6360_CHAN_MAX),
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};
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static irqreturn_t mt6360_adc_trigger_handler(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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struct iio_dev *indio_dev = pf->indio_dev;
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struct mt6360_adc_data *mad = iio_priv(indio_dev);
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struct {
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u16 values[MT6360_CHAN_MAX];
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int64_t timestamp;
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} data __aligned(8);
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int i = 0, bit, val, ret;
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memset(&data, 0, sizeof(data));
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for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->masklength) {
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ret = mt6360_adc_read_channel(mad, bit, &val);
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if (ret < 0) {
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dev_warn(&indio_dev->dev, "Failed to get channel %d conversion val\n", bit);
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goto out;
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}
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data.values[i++] = val;
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}
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iio_push_to_buffers_with_timestamp(indio_dev, &data, iio_get_time_ns(indio_dev));
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out:
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iio_trigger_notify_done(indio_dev->trig);
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return IRQ_HANDLED;
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}
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static inline int mt6360_adc_reset(struct mt6360_adc_data *info)
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{
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__be16 adc_enable;
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ktime_t all_off_time;
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int i, ret;
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/* Clear ADC idle wait time to 0 */
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ret = regmap_write(info->regmap, MT6360_REG_PMUADCIDLET, 0);
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if (ret)
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return ret;
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/* Only keep ADC enable, but keep all channels off */
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adc_enable = cpu_to_be16(MT6360_ADCEN_MASK);
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ret = regmap_raw_write(info->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable));
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if (ret)
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return ret;
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/* Reset all channel off time to the current one */
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all_off_time = ktime_get();
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for (i = 0; i < MT6360_CHAN_MAX; i++)
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info->last_off_timestamps[i] = all_off_time;
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return 0;
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}
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static int mt6360_adc_probe(struct platform_device *pdev)
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{
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struct mt6360_adc_data *mad;
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struct regmap *regmap;
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struct iio_dev *indio_dev;
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int ret;
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regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!regmap) {
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dev_err(&pdev->dev, "Failed to get parent regmap\n");
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return -ENODEV;
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}
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indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*mad));
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if (!indio_dev)
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return -ENOMEM;
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mad = iio_priv(indio_dev);
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mad->dev = &pdev->dev;
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mad->regmap = regmap;
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mutex_init(&mad->adc_lock);
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ret = mt6360_adc_reset(mad);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to reset adc\n");
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return ret;
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}
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indio_dev->name = dev_name(&pdev->dev);
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indio_dev->info = &mt6360_adc_iio_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = mt6360_adc_channels;
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indio_dev->num_channels = ARRAY_SIZE(mt6360_adc_channels);
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ret = devm_iio_triggered_buffer_setup(&pdev->dev, indio_dev, NULL,
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mt6360_adc_trigger_handler, NULL);
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if (ret) {
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dev_err(&pdev->dev, "Failed to allocate iio trigger buffer\n");
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return ret;
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}
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return devm_iio_device_register(&pdev->dev, indio_dev);
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}
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static const struct of_device_id __maybe_unused mt6360_adc_of_id[] = {
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{ .compatible = "mediatek,mt6360-adc", },
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{}
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};
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MODULE_DEVICE_TABLE(of, mt6360_adc_of_id);
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static struct platform_driver mt6360_adc_driver = {
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.driver = {
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.name = "mt6360-adc",
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.of_match_table = mt6360_adc_of_id,
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},
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.probe = mt6360_adc_probe,
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};
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module_platform_driver(mt6360_adc_driver);
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MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>");
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MODULE_DESCRIPTION("MT6360 ADC Driver");
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MODULE_LICENSE("GPL v2");
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