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![Sergiu Cuciurean](/assets/img/avatar_default.png)
As part of the general cleanup of indio_dev->mlock, this change replaces it with a local lock on the device's state structure. This is part of a bigger cleanup. Link: https://lore.kernel.org/linux-iio/CA+U=Dsoo6YABe5ODLp+eFNPGFDjk5ZeQEceGkqjxXcVEhLWubw@mail.gmail.com/ Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com> Signed-off-by: Mircea Caprioru <mircea.caprioru@analog.com> Link: https://lore.kernel.org/r/20200928131333.36646-1-mircea.caprioru@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
401 lines
9.5 KiB
C
401 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* ST SPEAr ADC driver
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*
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* Copyright 2012 Stefan Roese <sr@denx.de>
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/completion.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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/* SPEAR registers definitions */
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#define SPEAR600_ADC_SCAN_RATE_LO(x) ((x) & 0xFFFF)
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#define SPEAR600_ADC_SCAN_RATE_HI(x) (((x) >> 0x10) & 0xFFFF)
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#define SPEAR_ADC_CLK_LOW(x) (((x) & 0xf) << 0)
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#define SPEAR_ADC_CLK_HIGH(x) (((x) & 0xf) << 4)
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/* Bit definitions for SPEAR_ADC_STATUS */
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#define SPEAR_ADC_STATUS_START_CONVERSION BIT(0)
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#define SPEAR_ADC_STATUS_CHANNEL_NUM(x) ((x) << 1)
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#define SPEAR_ADC_STATUS_ADC_ENABLE BIT(4)
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#define SPEAR_ADC_STATUS_AVG_SAMPLE(x) ((x) << 5)
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#define SPEAR_ADC_STATUS_VREF_INTERNAL BIT(9)
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#define SPEAR_ADC_DATA_MASK 0x03ff
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#define SPEAR_ADC_DATA_BITS 10
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#define SPEAR_ADC_MOD_NAME "spear-adc"
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#define SPEAR_ADC_CHANNEL_NUM 8
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#define SPEAR_ADC_CLK_MIN 2500000
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#define SPEAR_ADC_CLK_MAX 20000000
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struct adc_regs_spear3xx {
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u32 status;
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u32 average;
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u32 scan_rate;
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u32 clk; /* Not avail for 1340 & 1310 */
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u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
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u32 ch_data[SPEAR_ADC_CHANNEL_NUM];
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};
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struct chan_data {
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u32 lsb;
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u32 msb;
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};
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struct adc_regs_spear6xx {
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u32 status;
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u32 pad[2];
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u32 clk;
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u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
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struct chan_data ch_data[SPEAR_ADC_CHANNEL_NUM];
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u32 scan_rate_lo;
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u32 scan_rate_hi;
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struct chan_data average;
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};
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struct spear_adc_state {
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struct device_node *np;
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struct adc_regs_spear3xx __iomem *adc_base_spear3xx;
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struct adc_regs_spear6xx __iomem *adc_base_spear6xx;
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struct clk *clk;
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struct completion completion;
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/*
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* Lock to protect the device state during a potential concurrent
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* read access from userspace. Reading a raw value requires a sequence
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* of register writes, then a wait for a completion callback,
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* and finally a register read, during which userspace could issue
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* another read request. This lock protects a read access from
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* ocurring before another one has finished.
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*/
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struct mutex lock;
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u32 current_clk;
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u32 sampling_freq;
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u32 avg_samples;
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u32 vref_external;
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u32 value;
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};
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/*
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* Functions to access some SPEAr ADC register. Abstracted into
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* static inline functions, because of different register offsets
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* on different SoC variants (SPEAr300 vs SPEAr600 etc).
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*/
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static void spear_adc_set_status(struct spear_adc_state *st, u32 val)
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{
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__raw_writel(val, &st->adc_base_spear6xx->status);
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}
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static void spear_adc_set_clk(struct spear_adc_state *st, u32 val)
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{
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u32 clk_high, clk_low, count;
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u32 apb_clk = clk_get_rate(st->clk);
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count = DIV_ROUND_UP(apb_clk, val);
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clk_low = count / 2;
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clk_high = count - clk_low;
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st->current_clk = apb_clk / count;
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__raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high),
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&st->adc_base_spear6xx->clk);
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}
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static void spear_adc_set_ctrl(struct spear_adc_state *st, int n,
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u32 val)
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{
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__raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]);
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}
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static u32 spear_adc_get_average(struct spear_adc_state *st)
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{
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if (of_device_is_compatible(st->np, "st,spear600-adc")) {
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return __raw_readl(&st->adc_base_spear6xx->average.msb) &
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SPEAR_ADC_DATA_MASK;
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} else {
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return __raw_readl(&st->adc_base_spear3xx->average) &
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SPEAR_ADC_DATA_MASK;
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}
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}
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static void spear_adc_set_scanrate(struct spear_adc_state *st, u32 rate)
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{
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if (of_device_is_compatible(st->np, "st,spear600-adc")) {
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__raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate),
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&st->adc_base_spear6xx->scan_rate_lo);
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__raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate),
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&st->adc_base_spear6xx->scan_rate_hi);
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} else {
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__raw_writel(rate, &st->adc_base_spear3xx->scan_rate);
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}
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}
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static int spear_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long mask)
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{
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struct spear_adc_state *st = iio_priv(indio_dev);
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u32 status;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&st->lock);
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status = SPEAR_ADC_STATUS_CHANNEL_NUM(chan->channel) |
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SPEAR_ADC_STATUS_AVG_SAMPLE(st->avg_samples) |
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SPEAR_ADC_STATUS_START_CONVERSION |
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SPEAR_ADC_STATUS_ADC_ENABLE;
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if (st->vref_external == 0)
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status |= SPEAR_ADC_STATUS_VREF_INTERNAL;
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spear_adc_set_status(st, status);
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wait_for_completion(&st->completion); /* set by ISR */
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*val = st->value;
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mutex_unlock(&st->lock);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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*val = st->vref_external;
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*val2 = SPEAR_ADC_DATA_BITS;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_SAMP_FREQ:
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*val = st->current_clk;
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return IIO_VAL_INT;
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}
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return -EINVAL;
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}
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static int spear_adc_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val,
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int val2,
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long mask)
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{
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struct spear_adc_state *st = iio_priv(indio_dev);
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int ret = 0;
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if (mask != IIO_CHAN_INFO_SAMP_FREQ)
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return -EINVAL;
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mutex_lock(&st->lock);
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if ((val < SPEAR_ADC_CLK_MIN) ||
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(val > SPEAR_ADC_CLK_MAX) ||
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(val2 != 0)) {
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ret = -EINVAL;
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goto out;
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}
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spear_adc_set_clk(st, val);
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out:
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mutex_unlock(&st->lock);
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return ret;
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}
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#define SPEAR_ADC_CHAN(idx) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
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.channel = idx, \
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}
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static const struct iio_chan_spec spear_adc_iio_channels[] = {
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SPEAR_ADC_CHAN(0),
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SPEAR_ADC_CHAN(1),
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SPEAR_ADC_CHAN(2),
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SPEAR_ADC_CHAN(3),
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SPEAR_ADC_CHAN(4),
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SPEAR_ADC_CHAN(5),
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SPEAR_ADC_CHAN(6),
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SPEAR_ADC_CHAN(7),
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};
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static irqreturn_t spear_adc_isr(int irq, void *dev_id)
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{
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struct spear_adc_state *st = dev_id;
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/* Read value to clear IRQ */
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st->value = spear_adc_get_average(st);
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complete(&st->completion);
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return IRQ_HANDLED;
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}
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static int spear_adc_configure(struct spear_adc_state *st)
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{
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int i;
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/* Reset ADC core */
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spear_adc_set_status(st, 0);
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__raw_writel(0, &st->adc_base_spear6xx->clk);
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for (i = 0; i < 8; i++)
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spear_adc_set_ctrl(st, i, 0);
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spear_adc_set_scanrate(st, 0);
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spear_adc_set_clk(st, st->sampling_freq);
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return 0;
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}
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static const struct iio_info spear_adc_info = {
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.read_raw = &spear_adc_read_raw,
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.write_raw = &spear_adc_write_raw,
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};
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static int spear_adc_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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struct spear_adc_state *st;
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struct iio_dev *indio_dev = NULL;
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int ret = -ENODEV;
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int irq;
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indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state));
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if (!indio_dev) {
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dev_err(dev, "failed allocating iio device\n");
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return -ENOMEM;
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}
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st = iio_priv(indio_dev);
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mutex_init(&st->lock);
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st->np = np;
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/*
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* SPEAr600 has a different register layout than other SPEAr SoC's
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* (e.g. SPEAr3xx). Let's provide two register base addresses
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* to support multi-arch kernels.
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*/
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st->adc_base_spear6xx = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(st->adc_base_spear6xx))
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return PTR_ERR(st->adc_base_spear6xx);
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st->adc_base_spear3xx =
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(struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx;
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st->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(st->clk)) {
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dev_err(dev, "failed getting clock\n");
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return PTR_ERR(st->clk);
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}
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ret = clk_prepare_enable(st->clk);
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if (ret) {
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dev_err(dev, "failed enabling clock\n");
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return ret;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0) {
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ret = -EINVAL;
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goto errout2;
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}
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ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME,
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st);
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if (ret < 0) {
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dev_err(dev, "failed requesting interrupt\n");
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goto errout2;
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}
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if (of_property_read_u32(np, "sampling-frequency",
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&st->sampling_freq)) {
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dev_err(dev, "sampling-frequency missing in DT\n");
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ret = -EINVAL;
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goto errout2;
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}
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/*
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* Optional avg_samples defaults to 0, resulting in single data
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* conversion
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*/
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of_property_read_u32(np, "average-samples", &st->avg_samples);
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/*
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* Optional vref_external defaults to 0, resulting in internal vref
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* selection
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*/
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of_property_read_u32(np, "vref-external", &st->vref_external);
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spear_adc_configure(st);
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platform_set_drvdata(pdev, indio_dev);
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init_completion(&st->completion);
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indio_dev->name = SPEAR_ADC_MOD_NAME;
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indio_dev->info = &spear_adc_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = spear_adc_iio_channels;
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indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels);
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ret = iio_device_register(indio_dev);
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if (ret)
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goto errout2;
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dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq);
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return 0;
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errout2:
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clk_disable_unprepare(st->clk);
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return ret;
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}
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static int spear_adc_remove(struct platform_device *pdev)
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{
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struct iio_dev *indio_dev = platform_get_drvdata(pdev);
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struct spear_adc_state *st = iio_priv(indio_dev);
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iio_device_unregister(indio_dev);
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clk_disable_unprepare(st->clk);
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return 0;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id spear_adc_dt_ids[] = {
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{ .compatible = "st,spear600-adc", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, spear_adc_dt_ids);
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#endif
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static struct platform_driver spear_adc_driver = {
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.probe = spear_adc_probe,
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.remove = spear_adc_remove,
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.driver = {
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.name = SPEAR_ADC_MOD_NAME,
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.of_match_table = of_match_ptr(spear_adc_dt_ids),
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},
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};
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module_platform_driver(spear_adc_driver);
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MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
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MODULE_DESCRIPTION("SPEAr ADC driver");
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MODULE_LICENSE("GPL");
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