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2e27041296
This patch removes the restriction of having a limited amount of only
four active tds on one endpoint. We use the linked list implementation
to manage all tds which get added and removed by hardware_{en,de}queue.
The removal of this restriction adds the driver to run into a hardware
errata. It's possible that the hardware will still address an transfer
descriptor that already got cleaned up. To solve this the patch also
postpone the cleanup of processed tds by one.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
306 lines
7.4 KiB
C
306 lines
7.4 KiB
C
/*
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* ci.h - common structures, functions, and macros of the ChipIdea driver
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*
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* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
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*
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* Author: David Lopo
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
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#define __DRIVERS_USB_CHIPIDEA_CI_H
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#include <linux/list.h>
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#include <linux/irqreturn.h>
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#include <linux/usb.h>
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#include <linux/usb/gadget.h>
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/******************************************************************************
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* DEFINE
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*****************************************************************************/
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#define TD_PAGE_COUNT 5
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#define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */
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#define ENDPT_MAX 32
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/******************************************************************************
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* STRUCTURES
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*****************************************************************************/
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/**
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* struct ci13xxx_ep - endpoint representation
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* @ep: endpoint structure for gadget drivers
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* @dir: endpoint direction (TX/RX)
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* @num: endpoint number
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* @type: endpoint type
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* @name: string description of the endpoint
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* @qh: queue head for this endpoint
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* @wedge: is the endpoint wedged
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* @ci: pointer to the controller
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* @lock: pointer to controller's spinlock
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* @td_pool: pointer to controller's TD pool
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*/
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struct ci13xxx_ep {
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struct usb_ep ep;
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u8 dir;
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u8 num;
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u8 type;
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char name[16];
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struct {
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struct list_head queue;
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struct ci13xxx_qh *ptr;
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dma_addr_t dma;
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} qh;
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int wedge;
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/* global resources */
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struct ci13xxx *ci;
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spinlock_t *lock;
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struct dma_pool *td_pool;
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struct td_node *pending_td;
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};
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enum ci_role {
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CI_ROLE_HOST = 0,
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CI_ROLE_GADGET,
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CI_ROLE_END,
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};
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/**
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* struct ci_role_driver - host/gadget role driver
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* start: start this role
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* stop: stop this role
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* irq: irq handler for this role
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* name: role name string (host/gadget)
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*/
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struct ci_role_driver {
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int (*start)(struct ci13xxx *);
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void (*stop)(struct ci13xxx *);
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irqreturn_t (*irq)(struct ci13xxx *);
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const char *name;
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};
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/**
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* struct hw_bank - hardware register mapping representation
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* @lpm: set if the device is LPM capable
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* @phys: physical address of the controller's registers
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* @abs: absolute address of the beginning of register window
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* @cap: capability registers
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* @op: operational registers
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* @size: size of the register window
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* @regmap: register lookup table
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*/
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struct hw_bank {
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unsigned lpm;
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resource_size_t phys;
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void __iomem *abs;
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void __iomem *cap;
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void __iomem *op;
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size_t size;
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void __iomem **regmap;
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};
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/**
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* struct ci13xxx - chipidea device representation
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* @dev: pointer to parent device
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* @lock: access synchronization
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* @hw_bank: hardware register mapping
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* @irq: IRQ number
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* @roles: array of supported roles for this controller
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* @role: current role
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* @is_otg: if the device is otg-capable
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* @work: work for role changing
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* @wq: workqueue thread
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* @qh_pool: allocation pool for queue heads
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* @td_pool: allocation pool for transfer descriptors
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* @gadget: device side representation for peripheral controller
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* @driver: gadget driver
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* @hw_ep_max: total number of endpoints supported by hardware
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* @ci13xxx_ep: array of endpoints
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* @ep0_dir: ep0 direction
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* @ep0out: pointer to ep0 OUT endpoint
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* @ep0in: pointer to ep0 IN endpoint
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* @status: ep0 status request
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* @setaddr: if we should set the address on status completion
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* @address: usb address received from the host
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* @remote_wakeup: host-enabled remote wakeup
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* @suspended: suspended by host
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* @test_mode: the selected test mode
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* @platdata: platform specific information supplied by parent device
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* @vbus_active: is VBUS active
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* @transceiver: pointer to USB PHY, if any
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* @hcd: pointer to usb_hcd for ehci host driver
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* @debugfs: root dentry for this controller in debugfs
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*/
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struct ci13xxx {
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struct device *dev;
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spinlock_t lock;
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struct hw_bank hw_bank;
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int irq;
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struct ci_role_driver *roles[CI_ROLE_END];
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enum ci_role role;
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bool is_otg;
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struct work_struct work;
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struct workqueue_struct *wq;
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struct dma_pool *qh_pool;
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struct dma_pool *td_pool;
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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unsigned hw_ep_max;
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struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX];
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u32 ep0_dir;
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struct ci13xxx_ep *ep0out, *ep0in;
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struct usb_request *status;
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bool setaddr;
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u8 address;
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u8 remote_wakeup;
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u8 suspended;
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u8 test_mode;
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struct ci13xxx_platform_data *platdata;
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int vbus_active;
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/* FIXME: some day, we'll not use global phy */
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bool global_phy;
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struct usb_phy *transceiver;
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struct usb_hcd *hcd;
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struct dentry *debugfs;
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};
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static inline struct ci_role_driver *ci_role(struct ci13xxx *ci)
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{
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BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
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return ci->roles[ci->role];
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}
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static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role)
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{
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int ret;
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if (role >= CI_ROLE_END)
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return -EINVAL;
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if (!ci->roles[role])
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return -ENXIO;
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ret = ci->roles[role]->start(ci);
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if (!ret)
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ci->role = role;
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return ret;
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}
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static inline void ci_role_stop(struct ci13xxx *ci)
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{
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enum ci_role role = ci->role;
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if (role == CI_ROLE_END)
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return;
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ci->role = CI_ROLE_END;
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ci->roles[role]->stop(ci);
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}
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/******************************************************************************
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* REGISTERS
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*****************************************************************************/
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/* register size */
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#define REG_BITS (32)
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/* register indices */
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enum ci13xxx_regs {
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CAP_CAPLENGTH,
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CAP_HCCPARAMS,
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CAP_DCCPARAMS,
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CAP_TESTMODE,
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CAP_LAST = CAP_TESTMODE,
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OP_USBCMD,
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OP_USBSTS,
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OP_USBINTR,
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OP_DEVICEADDR,
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OP_ENDPTLISTADDR,
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OP_PORTSC,
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OP_DEVLC,
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OP_OTGSC,
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OP_USBMODE,
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OP_ENDPTSETUPSTAT,
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OP_ENDPTPRIME,
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OP_ENDPTFLUSH,
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OP_ENDPTSTAT,
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OP_ENDPTCOMPLETE,
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OP_ENDPTCTRL,
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/* endptctrl1..15 follow */
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OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
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};
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/**
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* hw_read: reads from a hw register
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* @reg: register index
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* @mask: bitfield mask
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*
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* This function returns register contents
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*/
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static inline u32 hw_read(struct ci13xxx *ci, enum ci13xxx_regs reg, u32 mask)
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{
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return ioread32(ci->hw_bank.regmap[reg]) & mask;
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}
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/**
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* hw_write: writes to a hw register
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* @reg: register index
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* @mask: bitfield mask
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* @data: new value
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*/
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static inline void hw_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
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u32 mask, u32 data)
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{
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if (~mask)
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data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
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| (data & mask);
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iowrite32(data, ci->hw_bank.regmap[reg]);
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}
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/**
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* hw_test_and_clear: tests & clears a hw register
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* @reg: register index
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* @mask: bitfield mask
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*
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* This function returns register contents
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*/
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static inline u32 hw_test_and_clear(struct ci13xxx *ci, enum ci13xxx_regs reg,
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u32 mask)
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{
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u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
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iowrite32(val, ci->hw_bank.regmap[reg]);
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return val;
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}
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/**
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* hw_test_and_write: tests & writes a hw register
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* @reg: register index
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* @mask: bitfield mask
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* @data: new value
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*
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* This function returns register contents
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*/
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static inline u32 hw_test_and_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
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u32 mask, u32 data)
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{
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u32 val = hw_read(ci, reg, ~0);
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hw_write(ci, reg, mask, data);
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return (val & mask) >> __ffs(mask);
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}
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int hw_device_reset(struct ci13xxx *ci, u32 mode);
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int hw_port_test_set(struct ci13xxx *ci, u8 mode);
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u8 hw_port_test_get(struct ci13xxx *ci);
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#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */
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