Deepak Sharma a8fb40966f x86: ACPI: cstate: Optimize C3 entry on AMD CPUs ... All Zen or newer CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause drop in performance for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly. Signed-off-by: Deepak Sharma <deepak.sharma@amd.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>		2021-10-01 20:44:31 +02:00
..
apei.c	x86/mce, cper: Pass x86 CPER through the MCA handling chain	2020-11-21 12:05:41 +01:00
boot.c	x86/ACPI: Don't add CPUs that are not online capable	2021-09-13 19:19:02 +02:00
cppc_msr.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
cstate.c	x86: ACPI: cstate: Optimize C3 entry on AMD CPUs	2021-10-01 20:44:31 +02:00
Makefile	x86/acpi: Support objtool validation in wakeup_64.S	2021-01-26 11:33:03 -06:00
sleep.c	x86: Fix various typos in comments	2021-03-18 15:31:53 +01:00
sleep.h	x86/acpi: make "asmlinkage" part first thing in the function definition	2020-03-14 10:29:07 +01:00
wakeup_32.S	x86/asm/32: Add ENDs to some functions and relabel with SYM_CODE_*	2019-10-18 11:58:33 +02:00
wakeup_64.S	kasan: remove redundant config option	2021-04-16 16:10:36 -07:00