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The Hantro mainline driver has been used in production since several years and was only kept as a staging driver due the stateless CODEC controls. Now that all the stateless CODEC controls have been moved out of staging, graduate the driver as well. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
39 lines
1 KiB
C
39 lines
1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Hantro VPU codec driver
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*
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
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* Jeffy Chen <jeffy.chen@rock-chips.com>
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* Copyright (C) 2019 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
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* Copyright (C) 2021 Collabora Ltd, Emil Velikov <emil.velikov@collabora.com>
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*/
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#include "hantro.h"
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#include "hantro_g1_regs.h"
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irqreturn_t hantro_g1_irq(int irq, void *dev_id)
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{
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struct hantro_dev *vpu = dev_id;
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enum vb2_buffer_state state;
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u32 status;
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status = vdpu_read(vpu, G1_REG_INTERRUPT);
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state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ?
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VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
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vdpu_write(vpu, 0, G1_REG_INTERRUPT);
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vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
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hantro_irq_done(vpu, state);
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return IRQ_HANDLED;
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}
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void hantro_g1_reset(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
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vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
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vdpu_write(vpu, 1, G1_REG_SOFT_RESET);
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}
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