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![Hannes Reinecke](/assets/img/avatar_default.png)
Signed-off-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
597 lines
16 KiB
C
597 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* sata_qstor.c - Pacific Digital Corporation QStor SATA
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*
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* Maintained by: Mark Lord <mlord@pobox.com>
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*
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* Copyright 2005 Pacific Digital Corporation.
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* (OSL/GPL code release authorized by Jalil Fadavi).
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/driver-api/libata.rst
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/gfp.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "sata_qstor"
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#define DRV_VERSION "0.09"
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enum {
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QS_MMIO_BAR = 4,
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QS_PORTS = 4,
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QS_MAX_PRD = LIBATA_MAX_PRD,
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QS_CPB_ORDER = 6,
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QS_CPB_BYTES = (1 << QS_CPB_ORDER),
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QS_PRD_BYTES = QS_MAX_PRD * 16,
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QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
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/* global register offsets */
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QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
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QS_HID_HPHY = 0x0004, /* host physical interface info */
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QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
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QS_HST_SFF = 0x0100, /* host status fifo offset */
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QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
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/* global control bits */
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QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
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QS_CNFG3_GSRST = 0x01, /* global chip reset */
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QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
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/* per-channel register offsets */
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QS_CCF_CPBA = 0x0710, /* chan CPB base address */
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QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
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QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
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QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
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QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
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QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
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QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
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QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
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QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
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/* channel control bits */
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QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
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QS_CTR0_CLER = (1 << 2), /* clear channel errors */
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QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
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QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
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QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
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/* pkt sub-field headers */
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QS_HCB_HDR = 0x01, /* Host Control Block header */
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QS_DCB_HDR = 0x02, /* Device Control Block header */
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/* pkt HCB flag bits */
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QS_HF_DIRO = (1 << 0), /* data DIRection Out */
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QS_HF_DAT = (1 << 3), /* DATa pkt */
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QS_HF_IEN = (1 << 4), /* Interrupt ENable */
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QS_HF_VLD = (1 << 5), /* VaLiD pkt */
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/* pkt DCB flag bits */
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QS_DF_PORD = (1 << 2), /* Pio OR Dma */
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QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
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/* PCI device IDs */
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board_2068_idx = 0, /* QStor 4-port SATA/RAID */
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};
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enum {
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QS_DMA_BOUNDARY = ~0UL
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};
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typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
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struct qs_port_priv {
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u8 *pkt;
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dma_addr_t pkt_dma;
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qs_state_t state;
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};
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static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
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static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
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static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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static int qs_port_start(struct ata_port *ap);
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static void qs_host_stop(struct ata_host *host);
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static enum ata_completion_errors qs_qc_prep(struct ata_queued_cmd *qc);
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static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
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static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
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static void qs_freeze(struct ata_port *ap);
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static void qs_thaw(struct ata_port *ap);
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static int qs_prereset(struct ata_link *link, unsigned long deadline);
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static void qs_error_handler(struct ata_port *ap);
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static struct scsi_host_template qs_ata_sht = {
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ATA_BASE_SHT(DRV_NAME),
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.sg_tablesize = QS_MAX_PRD,
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.dma_boundary = QS_DMA_BOUNDARY,
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};
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static struct ata_port_operations qs_ata_ops = {
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.inherits = &ata_sff_port_ops,
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.check_atapi_dma = qs_check_atapi_dma,
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.qc_prep = qs_qc_prep,
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.qc_issue = qs_qc_issue,
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.freeze = qs_freeze,
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.thaw = qs_thaw,
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.prereset = qs_prereset,
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.softreset = ATA_OP_NULL,
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.error_handler = qs_error_handler,
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.lost_interrupt = ATA_OP_NULL,
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.scr_read = qs_scr_read,
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.scr_write = qs_scr_write,
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.port_start = qs_port_start,
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.host_stop = qs_host_stop,
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};
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static const struct ata_port_info qs_port_info[] = {
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/* board_2068_idx */
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{
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.flags = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
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.pio_mask = ATA_PIO4_ONLY,
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.udma_mask = ATA_UDMA6,
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.port_ops = &qs_ata_ops,
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},
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};
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static const struct pci_device_id qs_ata_pci_tbl[] = {
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{ PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
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{ } /* terminate list */
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};
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static struct pci_driver qs_ata_pci_driver = {
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.name = DRV_NAME,
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.id_table = qs_ata_pci_tbl,
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.probe = qs_ata_init_one,
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.remove = ata_pci_remove_one,
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};
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static void __iomem *qs_mmio_base(struct ata_host *host)
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{
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return host->iomap[QS_MMIO_BAR];
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}
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static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
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{
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return 1; /* ATAPI DMA not supported */
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}
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static inline void qs_enter_reg_mode(struct ata_port *ap)
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{
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u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
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struct qs_port_priv *pp = ap->private_data;
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pp->state = qs_state_mmio;
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writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
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readb(chan + QS_CCT_CTR0); /* flush */
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}
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static inline void qs_reset_channel_logic(struct ata_port *ap)
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{
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u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
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writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
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readb(chan + QS_CCT_CTR0); /* flush */
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qs_enter_reg_mode(ap);
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}
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static void qs_freeze(struct ata_port *ap)
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{
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u8 __iomem *mmio_base = qs_mmio_base(ap->host);
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writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
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qs_enter_reg_mode(ap);
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}
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static void qs_thaw(struct ata_port *ap)
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{
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u8 __iomem *mmio_base = qs_mmio_base(ap->host);
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qs_enter_reg_mode(ap);
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writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
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}
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static int qs_prereset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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qs_reset_channel_logic(ap);
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return ata_sff_prereset(link, deadline);
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}
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static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
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{
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8));
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return 0;
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}
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static void qs_error_handler(struct ata_port *ap)
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{
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qs_enter_reg_mode(ap);
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ata_sff_error_handler(ap);
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}
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static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
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{
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));
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return 0;
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}
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static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
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{
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struct scatterlist *sg;
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struct ata_port *ap = qc->ap;
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struct qs_port_priv *pp = ap->private_data;
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u8 *prd = pp->pkt + QS_CPB_BYTES;
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unsigned int si;
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for_each_sg(qc->sg, sg, qc->n_elem, si) {
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u64 addr;
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u32 len;
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addr = sg_dma_address(sg);
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*(__le64 *)prd = cpu_to_le64(addr);
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prd += sizeof(u64);
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len = sg_dma_len(sg);
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*(__le32 *)prd = cpu_to_le32(len);
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prd += sizeof(u64);
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}
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return si;
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}
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static enum ata_completion_errors qs_qc_prep(struct ata_queued_cmd *qc)
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{
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struct qs_port_priv *pp = qc->ap->private_data;
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u8 dflags = QS_DF_PORD, *buf = pp->pkt;
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u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
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u64 addr;
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unsigned int nelem;
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qs_enter_reg_mode(qc->ap);
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if (qc->tf.protocol != ATA_PROT_DMA)
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return AC_ERR_OK;
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nelem = qs_fill_sg(qc);
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if ((qc->tf.flags & ATA_TFLAG_WRITE))
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hflags |= QS_HF_DIRO;
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if ((qc->tf.flags & ATA_TFLAG_LBA48))
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dflags |= QS_DF_ELBA;
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/* host control block (HCB) */
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buf[ 0] = QS_HCB_HDR;
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buf[ 1] = hflags;
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*(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
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*(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
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addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
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*(__le64 *)(&buf[16]) = cpu_to_le64(addr);
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/* device control block (DCB) */
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buf[24] = QS_DCB_HDR;
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buf[28] = dflags;
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/* frame information structure (FIS) */
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ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
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return AC_ERR_OK;
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}
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static inline void qs_packet_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
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writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
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wmb(); /* flush PRDs and pkt to memory */
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writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
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readl(chan + QS_CCT_CFF); /* flush */
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}
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static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
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{
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struct qs_port_priv *pp = qc->ap->private_data;
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switch (qc->tf.protocol) {
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case ATA_PROT_DMA:
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pp->state = qs_state_pkt;
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qs_packet_start(qc);
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return 0;
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case ATAPI_PROT_DMA:
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BUG();
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break;
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default:
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break;
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}
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pp->state = qs_state_mmio;
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return ata_sff_qc_issue(qc);
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}
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static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
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{
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qc->err_mask |= ac_err_mask(status);
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if (!qc->err_mask) {
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ata_qc_complete(qc);
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} else {
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struct ata_port *ap = qc->ap;
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struct ata_eh_info *ehi = &ap->link.eh_info;
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ata_ehi_clear_desc(ehi);
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ata_ehi_push_desc(ehi, "status 0x%02X", status);
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if (qc->err_mask == AC_ERR_DEV)
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ata_port_abort(ap);
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else
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ata_port_freeze(ap);
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}
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}
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static inline unsigned int qs_intr_pkt(struct ata_host *host)
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{
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unsigned int handled = 0;
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u8 sFFE;
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u8 __iomem *mmio_base = qs_mmio_base(host);
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do {
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u32 sff0 = readl(mmio_base + QS_HST_SFF);
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u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
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u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
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sFFE = sff1 >> 31; /* empty flag */
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if (sEVLD) {
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u8 sDST = sff0 >> 16; /* dev status */
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u8 sHST = sff1 & 0x3f; /* host status */
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unsigned int port_no = (sff1 >> 8) & 0x03;
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struct ata_port *ap = host->ports[port_no];
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struct qs_port_priv *pp = ap->private_data;
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struct ata_queued_cmd *qc;
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dev_dbg(host->dev, "SFF=%08x%08x: sHST=%d sDST=%02x\n",
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sff1, sff0, sHST, sDST);
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handled = 1;
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if (!pp || pp->state != qs_state_pkt)
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continue;
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qc = ata_qc_from_tag(ap, ap->link.active_tag);
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if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
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switch (sHST) {
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case 0: /* successful CPB */
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case 3: /* device error */
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qs_enter_reg_mode(qc->ap);
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qs_do_or_die(qc, sDST);
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break;
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default:
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break;
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}
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}
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}
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} while (!sFFE);
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return handled;
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}
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static inline unsigned int qs_intr_mmio(struct ata_host *host)
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{
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unsigned int handled = 0, port_no;
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for (port_no = 0; port_no < host->n_ports; ++port_no) {
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struct ata_port *ap = host->ports[port_no];
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struct qs_port_priv *pp = ap->private_data;
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struct ata_queued_cmd *qc;
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qc = ata_qc_from_tag(ap, ap->link.active_tag);
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if (!qc) {
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/*
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* The qstor hardware generates spurious
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* interrupts from time to time when switching
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* in and out of packet mode. There's no
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* obvious way to know if we're here now due
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* to that, so just ack the irq and pretend we
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* knew it was ours.. (ugh). This does not
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* affect packet mode.
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*/
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ata_sff_check_status(ap);
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handled = 1;
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continue;
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}
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if (!pp || pp->state != qs_state_mmio)
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continue;
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if (!(qc->tf.flags & ATA_TFLAG_POLLING))
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handled |= ata_sff_port_intr(ap, qc);
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}
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return handled;
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}
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static irqreturn_t qs_intr(int irq, void *dev_instance)
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{
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struct ata_host *host = dev_instance;
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unsigned int handled = 0;
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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handled = qs_intr_pkt(host) | qs_intr_mmio(host);
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spin_unlock_irqrestore(&host->lock, flags);
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return IRQ_RETVAL(handled);
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}
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static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
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{
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port->cmd_addr =
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port->data_addr = base + 0x400;
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port->error_addr =
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port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
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port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
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port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
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port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
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port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
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port->device_addr = base + 0x430;
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port->status_addr =
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port->command_addr = base + 0x438;
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port->altstatus_addr =
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port->ctl_addr = base + 0x440;
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port->scr_addr = base + 0xc00;
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}
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static int qs_port_start(struct ata_port *ap)
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{
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struct device *dev = ap->host->dev;
|
|
struct qs_port_priv *pp;
|
|
void __iomem *mmio_base = qs_mmio_base(ap->host);
|
|
void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
|
|
u64 addr;
|
|
|
|
pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
|
|
if (!pp)
|
|
return -ENOMEM;
|
|
pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
|
|
GFP_KERNEL);
|
|
if (!pp->pkt)
|
|
return -ENOMEM;
|
|
ap->private_data = pp;
|
|
|
|
qs_enter_reg_mode(ap);
|
|
addr = (u64)pp->pkt_dma;
|
|
writel((u32) addr, chan + QS_CCF_CPBA);
|
|
writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
|
|
return 0;
|
|
}
|
|
|
|
static void qs_host_stop(struct ata_host *host)
|
|
{
|
|
void __iomem *mmio_base = qs_mmio_base(host);
|
|
|
|
writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
|
|
writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
|
|
}
|
|
|
|
static void qs_host_init(struct ata_host *host, unsigned int chip_id)
|
|
{
|
|
void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
|
|
unsigned int port_no;
|
|
|
|
writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
|
|
writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
|
|
|
|
/* reset each channel in turn */
|
|
for (port_no = 0; port_no < host->n_ports; ++port_no) {
|
|
u8 __iomem *chan = mmio_base + (port_no * 0x4000);
|
|
writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
|
|
writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
|
|
readb(chan + QS_CCT_CTR0); /* flush */
|
|
}
|
|
writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
|
|
|
|
for (port_no = 0; port_no < host->n_ports; ++port_no) {
|
|
u8 __iomem *chan = mmio_base + (port_no * 0x4000);
|
|
/* set FIFO depths to same settings as Windows driver */
|
|
writew(32, chan + QS_CFC_HUFT);
|
|
writew(32, chan + QS_CFC_HDFT);
|
|
writew(10, chan + QS_CFC_DUFT);
|
|
writew( 8, chan + QS_CFC_DDFT);
|
|
/* set CPB size in bytes, as a power of two */
|
|
writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
|
|
}
|
|
writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
|
|
}
|
|
|
|
/*
|
|
* The QStor understands 64-bit buses, and uses 64-bit fields
|
|
* for DMA pointers regardless of bus width. We just have to
|
|
* make sure our DMA masks are set appropriately for whatever
|
|
* bridge lies between us and the QStor, and then the DMA mapping
|
|
* code will ensure we only ever "see" appropriate buffer addresses.
|
|
* If we're 32-bit limited somewhere, then our 64-bit fields will
|
|
* just end up with zeros in the upper 32-bits, without any special
|
|
* logic required outside of this routine (below).
|
|
*/
|
|
static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
|
|
{
|
|
u32 bus_info = readl(mmio_base + QS_HID_HPHY);
|
|
int dma_bits = (bus_info & QS_HPHY_64BIT) ? 64 : 32;
|
|
int rc;
|
|
|
|
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
|
|
if (rc)
|
|
dev_err(&pdev->dev, "%d-bit DMA enable failed\n", dma_bits);
|
|
return rc;
|
|
}
|
|
|
|
static int qs_ata_init_one(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
unsigned int board_idx = (unsigned int) ent->driver_data;
|
|
const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
|
|
struct ata_host *host;
|
|
int rc, port_no;
|
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION);
|
|
|
|
/* alloc host */
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
|
|
if (!host)
|
|
return -ENOMEM;
|
|
|
|
/* acquire resources and fill host */
|
|
rc = pcim_enable_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
|
|
return -ENODEV;
|
|
|
|
rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
|
|
if (rc)
|
|
return rc;
|
|
host->iomap = pcim_iomap_table(pdev);
|
|
|
|
rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
|
|
if (rc)
|
|
return rc;
|
|
|
|
for (port_no = 0; port_no < host->n_ports; ++port_no) {
|
|
struct ata_port *ap = host->ports[port_no];
|
|
unsigned int offset = port_no * 0x4000;
|
|
void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
|
|
|
|
qs_ata_setup_port(&ap->ioaddr, chan);
|
|
|
|
ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
|
|
ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
|
|
}
|
|
|
|
/* initialize adapter */
|
|
qs_host_init(host, board_idx);
|
|
|
|
pci_set_master(pdev);
|
|
return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
|
|
&qs_ata_sht);
|
|
}
|
|
|
|
module_pci_driver(qs_ata_pci_driver);
|
|
|
|
MODULE_AUTHOR("Mark Lord");
|
|
MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
|
|
MODULE_VERSION(DRV_VERSION);
|