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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-25 10:19:47 +00:00
![Jani Nikula](/assets/img/avatar_default.png)
Have only one if ladder for platforms and only one range check for size. Makes it easier to handle new platforms. Remove the use of negative return values in char, which might underflow to be positive for some negative error codes. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1445344713-1407-3-git-send-email-jani.nikula@intel.com
494 lines
13 KiB
C
494 lines
13 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include "i915_drv.h"
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#include "i915_reg.h"
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/**
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* DOC: csr support for dmc
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*
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* Display Context Save and Restore (CSR) firmware support added from gen9
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* onwards to drive newly added DMC (Display microcontroller) in display
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* engine to save and restore the state of display engine when it enter into
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* low-power state and comes back to normal.
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*
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* Firmware loading status will be one of the below states: FW_UNINITIALIZED,
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* FW_LOADED, FW_FAILED.
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*
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* Once the firmware is written into the registers status will be moved from
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* FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
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* be moved to FW_FAILED.
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*/
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#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
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#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
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MODULE_FIRMWARE(I915_CSR_SKL);
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MODULE_FIRMWARE(I915_CSR_BXT);
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#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
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#define CSR_MAX_FW_SIZE 0x2FFF
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#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
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struct intel_css_header {
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/* 0x09 for DMC */
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uint32_t module_type;
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/* Includes the DMC specific header in dwords */
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uint32_t header_len;
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/* always value would be 0x10000 */
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uint32_t header_ver;
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/* Not used */
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uint32_t module_id;
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/* Not used */
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uint32_t module_vendor;
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/* in YYYYMMDD format */
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uint32_t date;
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/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
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uint32_t size;
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/* Not used */
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uint32_t key_size;
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/* Not used */
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uint32_t modulus_size;
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/* Not used */
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uint32_t exponent_size;
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/* Not used */
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uint32_t reserved1[12];
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/* Major Minor */
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uint32_t version;
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/* Not used */
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uint32_t reserved2[8];
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/* Not used */
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uint32_t kernel_header_info;
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} __packed;
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struct intel_fw_info {
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uint16_t reserved1;
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/* Stepping (A, B, C, ..., *). * is a wildcard */
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char stepping;
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/* Sub-stepping (0, 1, ..., *). * is a wildcard */
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char substepping;
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uint32_t offset;
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uint32_t reserved2;
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} __packed;
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struct intel_package_header {
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/* DMC container header length in dwords */
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unsigned char header_len;
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/* always value would be 0x01 */
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unsigned char header_ver;
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unsigned char reserved[10];
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/* Number of valid entries in the FWInfo array below */
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uint32_t num_entries;
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struct intel_fw_info fw_info[20];
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} __packed;
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struct intel_dmc_header {
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/* always value would be 0x40403E3E */
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uint32_t signature;
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/* DMC binary header length */
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unsigned char header_len;
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/* 0x01 */
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unsigned char header_ver;
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/* Reserved */
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uint16_t dmcc_ver;
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/* Major, Minor */
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uint32_t project;
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/* Firmware program size (excluding header) in dwords */
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uint32_t fw_size;
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/* Major Minor version */
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uint32_t fw_version;
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/* Number of valid MMIO cycles present. */
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uint32_t mmio_count;
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/* MMIO address */
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uint32_t mmioaddr[8];
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/* MMIO data */
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uint32_t mmiodata[8];
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/* FW filename */
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unsigned char dfile[32];
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uint32_t reserved1[2];
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} __packed;
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struct stepping_info {
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char stepping;
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char substepping;
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};
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static const struct stepping_info skl_stepping_info[] = {
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{'A', '0'}, {'B', '0'}, {'C', '0'},
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{'D', '0'}, {'E', '0'}, {'F', '0'},
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{'G', '0'}, {'H', '0'}, {'I', '0'}
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};
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static const struct stepping_info bxt_stepping_info[] = {
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{'A', '0'}, {'A', '1'}, {'A', '2'},
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{'B', '0'}, {'B', '1'}, {'B', '2'}
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};
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static const struct stepping_info *intel_get_stepping_info(struct drm_device *dev)
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{
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const struct stepping_info *si;
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unsigned int size;
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if (IS_SKYLAKE(dev)) {
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size = ARRAY_SIZE(skl_stepping_info);
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si = skl_stepping_info;
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} else if (IS_BROXTON(dev)) {
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size = ARRAY_SIZE(bxt_stepping_info);
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si = bxt_stepping_info;
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} else {
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return NULL;
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}
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if (INTEL_REVID(dev) < size)
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return si + INTEL_REVID(dev);
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return NULL;
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}
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/**
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* intel_csr_load_status_get() - to get firmware loading status.
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* @dev_priv: i915 device.
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*
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* This function helps to get the firmware loading status.
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*
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* Return: Firmware loading status.
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*/
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enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
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{
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enum csr_state state;
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mutex_lock(&dev_priv->csr_lock);
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state = dev_priv->csr.state;
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mutex_unlock(&dev_priv->csr_lock);
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return state;
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}
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/**
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* intel_csr_load_status_set() - help to set firmware loading status.
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* @dev_priv: i915 device.
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* @state: enumeration of firmware loading status.
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*
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* Set the firmware loading status.
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*/
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void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
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enum csr_state state)
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{
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mutex_lock(&dev_priv->csr_lock);
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dev_priv->csr.state = state;
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mutex_unlock(&dev_priv->csr_lock);
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}
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/**
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* intel_csr_load_program() - write the firmware from memory to register.
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* @dev: drm device.
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*
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* CSR firmware is read from a .bin file and kept in internal memory one time.
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* Everytime display comes back from low power state this function is called to
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* copy the firmware from internal memory to registers.
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*/
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void intel_csr_load_program(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 *payload = dev_priv->csr.dmc_payload;
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uint32_t i, fw_size;
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if (!IS_GEN9(dev)) {
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DRM_ERROR("No CSR support available for this platform\n");
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return;
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}
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/*
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* FIXME: Firmware gets lost on S3/S4, but not when entering system
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* standby or suspend-to-idle (which is just like forced runtime pm).
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* Unfortunately the ACPI subsystem doesn't yet give us a way to
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* differentiate this, hence figure it out with this hack.
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*/
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if (I915_READ(CSR_PROGRAM(0)))
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return;
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mutex_lock(&dev_priv->csr_lock);
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fw_size = dev_priv->csr.dmc_fw_size;
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for (i = 0; i < fw_size; i++)
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I915_WRITE(CSR_PROGRAM(i), payload[i]);
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for (i = 0; i < dev_priv->csr.mmio_count; i++) {
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I915_WRITE(dev_priv->csr.mmioaddr[i],
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dev_priv->csr.mmiodata[i]);
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}
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dev_priv->csr.state = FW_LOADED;
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mutex_unlock(&dev_priv->csr_lock);
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}
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static void finish_csr_load(const struct firmware *fw, void *context)
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{
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struct drm_i915_private *dev_priv = context;
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struct drm_device *dev = dev_priv->dev;
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struct intel_css_header *css_header;
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struct intel_package_header *package_header;
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struct intel_dmc_header *dmc_header;
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struct intel_csr *csr = &dev_priv->csr;
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const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
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char stepping, substepping;
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uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
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uint32_t i;
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uint32_t *dmc_payload;
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bool fw_loaded = false;
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if (!fw)
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goto out;
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if (!stepping_info) {
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DRM_ERROR("Unknown stepping info, firmware loading failed\n");
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goto out;
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}
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stepping = stepping_info->stepping;
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substepping = stepping_info->substepping;
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/* Extract CSS Header information*/
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css_header = (struct intel_css_header *)fw->data;
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if (sizeof(struct intel_css_header) !=
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(css_header->header_len * 4)) {
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DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
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(css_header->header_len * 4));
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goto out;
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}
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csr->version = css_header->version;
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if (IS_SKYLAKE(dev) && csr->version < SKL_CSR_VERSION_REQUIRED) {
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DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
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" please upgrade to v%u.%u or later"
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" [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n",
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CSR_VERSION_MAJOR(csr->version),
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CSR_VERSION_MINOR(csr->version),
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CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
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CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
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goto out;
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}
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readcount += sizeof(struct intel_css_header);
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/* Extract Package Header information*/
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package_header = (struct intel_package_header *)
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&fw->data[readcount];
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if (sizeof(struct intel_package_header) !=
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(package_header->header_len * 4)) {
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DRM_ERROR("Firmware has wrong package header length %u bytes\n",
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(package_header->header_len * 4));
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goto out;
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}
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readcount += sizeof(struct intel_package_header);
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/* Search for dmc_offset to find firware binary. */
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for (i = 0; i < package_header->num_entries; i++) {
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if (package_header->fw_info[i].substepping == '*' &&
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stepping == package_header->fw_info[i].stepping) {
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dmc_offset = package_header->fw_info[i].offset;
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break;
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} else if (stepping == package_header->fw_info[i].stepping &&
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substepping == package_header->fw_info[i].substepping) {
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dmc_offset = package_header->fw_info[i].offset;
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break;
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} else if (package_header->fw_info[i].stepping == '*' &&
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package_header->fw_info[i].substepping == '*')
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dmc_offset = package_header->fw_info[i].offset;
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}
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if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
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DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
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goto out;
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}
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readcount += dmc_offset;
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/* Extract dmc_header information. */
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dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
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if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
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DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
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(dmc_header->header_len));
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goto out;
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}
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readcount += sizeof(struct intel_dmc_header);
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/* Cache the dmc header info. */
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if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
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DRM_ERROR("Firmware has wrong mmio count %u\n",
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dmc_header->mmio_count);
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goto out;
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}
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csr->mmio_count = dmc_header->mmio_count;
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for (i = 0; i < dmc_header->mmio_count; i++) {
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if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
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dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
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DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
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dmc_header->mmioaddr[i]);
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goto out;
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}
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csr->mmioaddr[i] = dmc_header->mmioaddr[i];
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csr->mmiodata[i] = dmc_header->mmiodata[i];
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}
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/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
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nbytes = dmc_header->fw_size * 4;
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if (nbytes > CSR_MAX_FW_SIZE) {
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DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
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goto out;
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}
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csr->dmc_fw_size = dmc_header->fw_size;
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csr->dmc_payload = kmalloc(nbytes, GFP_KERNEL);
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if (!csr->dmc_payload) {
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DRM_ERROR("Memory allocation failed for dmc payload\n");
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goto out;
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}
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dmc_payload = csr->dmc_payload;
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memcpy(dmc_payload, &fw->data[readcount], nbytes);
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/* load csr program during system boot, as needed for DC states */
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intel_csr_load_program(dev);
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fw_loaded = true;
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out:
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if (fw_loaded) {
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intel_runtime_pm_put(dev_priv);
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DRM_INFO("Finished loading %s (v%u.%u)\n",
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dev_priv->csr.fw_path,
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CSR_VERSION_MAJOR(csr->version),
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CSR_VERSION_MINOR(csr->version));
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} else {
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intel_csr_load_status_set(dev_priv, FW_FAILED);
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i915_firmware_load_error_print(csr->fw_path, 0);
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}
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release_firmware(fw);
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}
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/**
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* intel_csr_ucode_init() - initialize the firmware loading.
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* @dev: drm device.
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*
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* This function is called at the time of loading the display driver to read
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* firmware from a .bin file and copied into a internal memory.
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*/
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void intel_csr_ucode_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_csr *csr = &dev_priv->csr;
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int ret;
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if (!HAS_CSR(dev))
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return;
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if (IS_SKYLAKE(dev))
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csr->fw_path = I915_CSR_SKL;
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else if (IS_BROXTON(dev_priv))
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csr->fw_path = I915_CSR_BXT;
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else {
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DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
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intel_csr_load_status_set(dev_priv, FW_FAILED);
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return;
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}
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DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
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/*
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* Obtain a runtime pm reference, until CSR is loaded,
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* to avoid entering runtime-suspend.
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*/
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intel_runtime_pm_get(dev_priv);
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/* CSR supported for platform, load firmware */
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ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path,
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&dev_priv->dev->pdev->dev,
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GFP_KERNEL, dev_priv,
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finish_csr_load);
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if (ret) {
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i915_firmware_load_error_print(csr->fw_path, ret);
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intel_csr_load_status_set(dev_priv, FW_FAILED);
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}
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}
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/**
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* intel_csr_ucode_fini() - unload the CSR firmware.
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* @dev: drm device.
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*
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* Firmmware unloading includes freeing the internal momory and reset the
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* firmware loading status.
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*/
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void intel_csr_ucode_fini(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (!HAS_CSR(dev))
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return;
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intel_csr_load_status_set(dev_priv, FW_FAILED);
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kfree(dev_priv->csr.dmc_payload);
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}
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void assert_csr_loaded(struct drm_i915_private *dev_priv)
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{
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WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
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"CSR is not loaded.\n");
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WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
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"CSR program storage start is NULL\n");
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WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
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WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
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}
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