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0242132da2
When config pci_ops.read() can detect failed PCI transactions, the data returned to the CPU is PCI_ERROR_RESPONSE (~0 or 0xffffffff). Obviously a successful PCI config read may *also* return that data if a config register happens to contain ~0, so it doesn't definitively indicate an error unless we know the register cannot contain ~0. Use PCI_POSSIBLE_ERROR() to check the response we get when we read data from hardware. This unifies PCI error response checking and makes error checks consistent and easier to find. Compile tested only. Link: https://lore.kernel.org/r/9b0632f1f183432149f495cf12bdd5a72cc597a4.1637243717.git.naveennaidu479@gmail.com Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
404 lines
11 KiB
C
404 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCI Express Downstream Port Containment services driver
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* Author: Keith Busch <keith.busch@intel.com>
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*
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* Copyright (C) 2016 Intel Corp.
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*/
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#define dev_fmt(fmt) "DPC: " fmt
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#include <linux/aer.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include "portdrv.h"
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#include "../pci.h"
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static const char * const rp_pio_error_string[] = {
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"Configuration Request received UR Completion", /* Bit Position 0 */
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"Configuration Request received CA Completion", /* Bit Position 1 */
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"Configuration Request Completion Timeout", /* Bit Position 2 */
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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"I/O Request received UR Completion", /* Bit Position 8 */
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"I/O Request received CA Completion", /* Bit Position 9 */
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"I/O Request Completion Timeout", /* Bit Position 10 */
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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"Memory Request received UR Completion", /* Bit Position 16 */
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"Memory Request received CA Completion", /* Bit Position 17 */
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"Memory Request Completion Timeout", /* Bit Position 18 */
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};
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void pci_save_dpc_state(struct pci_dev *dev)
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{
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struct pci_cap_saved_state *save_state;
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u16 *cap;
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if (!pci_is_pcie(dev))
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return;
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save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
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if (!save_state)
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return;
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cap = (u16 *)&save_state->cap.data[0];
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pci_read_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, cap);
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}
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void pci_restore_dpc_state(struct pci_dev *dev)
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{
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struct pci_cap_saved_state *save_state;
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u16 *cap;
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if (!pci_is_pcie(dev))
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return;
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save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
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if (!save_state)
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return;
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cap = (u16 *)&save_state->cap.data[0];
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pci_write_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, *cap);
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}
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static DECLARE_WAIT_QUEUE_HEAD(dpc_completed_waitqueue);
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#ifdef CONFIG_HOTPLUG_PCI_PCIE
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static bool dpc_completed(struct pci_dev *pdev)
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{
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u16 status;
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pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS, &status);
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if ((!PCI_POSSIBLE_ERROR(status)) && (status & PCI_EXP_DPC_STATUS_TRIGGER))
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return false;
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if (test_bit(PCI_DPC_RECOVERING, &pdev->priv_flags))
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return false;
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return true;
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}
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/**
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* pci_dpc_recovered - whether DPC triggered and has recovered successfully
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* @pdev: PCI device
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*
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* Return true if DPC was triggered for @pdev and has recovered successfully.
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* Wait for recovery if it hasn't completed yet. Called from the PCIe hotplug
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* driver to recognize and ignore Link Down/Up events caused by DPC.
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*/
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bool pci_dpc_recovered(struct pci_dev *pdev)
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{
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struct pci_host_bridge *host;
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if (!pdev->dpc_cap)
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return false;
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/*
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* Synchronization between hotplug and DPC is not supported
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* if DPC is owned by firmware and EDR is not enabled.
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*/
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host = pci_find_host_bridge(pdev->bus);
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if (!host->native_dpc && !IS_ENABLED(CONFIG_PCIE_EDR))
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return false;
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/*
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* Need a timeout in case DPC never completes due to failure of
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* dpc_wait_rp_inactive(). The spec doesn't mandate a time limit,
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* but reports indicate that DPC completes within 4 seconds.
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*/
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wait_event_timeout(dpc_completed_waitqueue, dpc_completed(pdev),
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msecs_to_jiffies(4000));
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return test_and_clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
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}
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#endif /* CONFIG_HOTPLUG_PCI_PCIE */
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static int dpc_wait_rp_inactive(struct pci_dev *pdev)
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{
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unsigned long timeout = jiffies + HZ;
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u16 cap = pdev->dpc_cap, status;
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
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while (status & PCI_EXP_DPC_RP_BUSY &&
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!time_after(jiffies, timeout)) {
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msleep(10);
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
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}
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if (status & PCI_EXP_DPC_RP_BUSY) {
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pci_warn(pdev, "root port still busy\n");
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return -EBUSY;
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}
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return 0;
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}
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pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
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{
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pci_ers_result_t ret;
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u16 cap;
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set_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
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/*
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* DPC disables the Link automatically in hardware, so it has
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* already been reset by the time we get here.
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*/
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cap = pdev->dpc_cap;
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/*
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* Wait until the Link is inactive, then clear DPC Trigger Status
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* to allow the Port to leave DPC.
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*/
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if (!pcie_wait_for_link(pdev, false))
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pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
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if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) {
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clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
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ret = PCI_ERS_RESULT_DISCONNECT;
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goto out;
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}
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pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
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PCI_EXP_DPC_STATUS_TRIGGER);
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if (!pcie_wait_for_link(pdev, true)) {
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pci_info(pdev, "Data Link Layer Link Active not set in 1000 msec\n");
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clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
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ret = PCI_ERS_RESULT_DISCONNECT;
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} else {
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set_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
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ret = PCI_ERS_RESULT_RECOVERED;
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}
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out:
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clear_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
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wake_up_all(&dpc_completed_waitqueue);
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return ret;
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}
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static void dpc_process_rp_pio_error(struct pci_dev *pdev)
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{
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u16 cap = pdev->dpc_cap, dpc_status, first_error;
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u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
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int i;
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
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pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
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status, mask);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
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pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
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sev, syserr, exc);
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/* Get First Error Pointer */
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
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first_error = (dpc_status & 0x1f00) >> 8;
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for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
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if ((status & ~mask) & (1 << i))
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pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
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first_error == i ? " (First)" : "");
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}
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if (pdev->dpc_rp_log_size < 4)
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goto clear_status;
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
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&dw0);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
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&dw1);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
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&dw2);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
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&dw3);
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pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",
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dw0, dw1, dw2, dw3);
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if (pdev->dpc_rp_log_size < 5)
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goto clear_status;
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
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pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);
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for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) {
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pci_read_config_dword(pdev,
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cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
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pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
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}
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clear_status:
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pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
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}
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static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev,
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struct aer_err_info *info)
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{
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int pos = dev->aer_cap;
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u32 status, mask, sev;
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask);
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status &= ~mask;
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if (!status)
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return 0;
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);
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status &= sev;
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if (status)
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info->severity = AER_FATAL;
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else
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info->severity = AER_NONFATAL;
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return 1;
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}
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void dpc_process_error(struct pci_dev *pdev)
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{
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u16 cap = pdev->dpc_cap, status, source, reason, ext_reason;
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struct aer_err_info info;
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
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pci_info(pdev, "containment event, status:%#06x source:%#06x\n",
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status, source);
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reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
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ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
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pci_warn(pdev, "%s detected\n",
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(reason == 0) ? "unmasked uncorrectable error" :
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(reason == 1) ? "ERR_NONFATAL" :
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(reason == 2) ? "ERR_FATAL" :
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(ext_reason == 0) ? "RP PIO error" :
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(ext_reason == 1) ? "software trigger" :
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"reserved error");
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/* show RP PIO error detail information */
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if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0)
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dpc_process_rp_pio_error(pdev);
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else if (reason == 0 &&
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dpc_get_aer_uncorrect_severity(pdev, &info) &&
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aer_get_device_error_info(pdev, &info)) {
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aer_print_error(pdev, &info);
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pci_aer_clear_nonfatal_status(pdev);
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pci_aer_clear_fatal_status(pdev);
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}
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}
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static irqreturn_t dpc_handler(int irq, void *context)
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{
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struct pci_dev *pdev = context;
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dpc_process_error(pdev);
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/* We configure DPC so it only triggers on ERR_FATAL */
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pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link);
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return IRQ_HANDLED;
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}
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static irqreturn_t dpc_irq(int irq, void *context)
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{
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struct pci_dev *pdev = context;
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u16 cap = pdev->dpc_cap, status;
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
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if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || PCI_POSSIBLE_ERROR(status))
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return IRQ_NONE;
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pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
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PCI_EXP_DPC_STATUS_INTERRUPT);
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if (status & PCI_EXP_DPC_STATUS_TRIGGER)
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return IRQ_WAKE_THREAD;
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return IRQ_HANDLED;
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}
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void pci_dpc_init(struct pci_dev *pdev)
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{
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u16 cap;
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pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
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if (!pdev->dpc_cap)
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return;
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pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
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if (!(cap & PCI_EXP_DPC_CAP_RP_EXT))
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return;
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pdev->dpc_rp_extensions = true;
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pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
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if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
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pci_err(pdev, "RP PIO log size %u is invalid\n",
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pdev->dpc_rp_log_size);
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pdev->dpc_rp_log_size = 0;
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}
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}
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#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
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static int dpc_probe(struct pcie_device *dev)
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{
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struct pci_dev *pdev = dev->port;
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struct device *device = &dev->device;
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int status;
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u16 ctl, cap;
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if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)
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return -ENOTSUPP;
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status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
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dpc_handler, IRQF_SHARED,
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"pcie-dpc", pdev);
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if (status) {
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pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
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status);
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return status;
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}
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pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
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pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
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ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
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pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
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pci_info(pdev, "enabled with IRQ %d\n", dev->irq);
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pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
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cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
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FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
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FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size,
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FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
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pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
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return status;
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}
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static void dpc_remove(struct pcie_device *dev)
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{
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struct pci_dev *pdev = dev->port;
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u16 ctl;
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pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
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ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN);
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pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
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}
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static struct pcie_port_service_driver dpcdriver = {
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.name = "dpc",
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.port_type = PCIE_ANY_PORT,
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.service = PCIE_PORT_SERVICE_DPC,
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.probe = dpc_probe,
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.remove = dpc_remove,
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};
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int __init pcie_dpc_init(void)
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{
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return pcie_port_service_register(&dpcdriver);
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}
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