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3a715e8040
FPU_STATUS register contains FP exception flags bits which are updated
by core as side-effect of FP instructions but can also be manually
wiggled such as by glibc C99 functions fe{raise,clear,test}except() etc.
To effect the update, the programming model requires OR'ing FWE
bit (31). This bit is write-only and RAZ, meaning it is effectively
auto-cleared after write and thus needs to be set everytime: which
is how glibc implements this.
However there's another usecase of FPU_STATUS update, at the time of
Linux task switch when incoming task value needs to be programmed into
the register. This was added as part of f45ba2bd6d ("ARCv2:
fpu: preserve userspace fpu state") which missed OR'ing FWE bit,
meaning the new value is effectively not being written at all.
This patch remedies that.
Interestingly, this snafu was not caught in interm glibc testing as the
race window which relies on a specific exception bit to be set/clear is
really small specially when it nvolves context switch.
Fortunately this was caught by glibc's math/test-fenv-tls test which
repeatedly set/clear exception flags in a big loop, concurrently in main
program and also in a thread.
Fixes: https://github.com/foss-for-synopsys-dwc-arc-processors/linux/issues/54
Fixes: f45ba2bd6d ("ARCv2: fpu: preserve userspace fpu state")
Cc: stable@vger.kernel.org #5.6+
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
82 lines
2.4 KiB
C
82 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* fpu.c - save/restore of Floating Point Unit Registers on task switch
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#include <linux/sched.h>
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#include <asm/fpu.h>
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#ifdef CONFIG_ISA_ARCOMPACT
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/*
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* To save/restore FPU regs, simplest scheme would use LR/SR insns.
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* However since SR serializes the pipeline, an alternate "hack" can be used
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* which uses the FPU Exchange insn (DEXCL) to r/w FPU regs.
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*
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* Store to 64bit dpfp1 reg from a pair of core regs:
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* dexcl1 0, r1, r0 ; where r1:r0 is the 64 bit val
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*
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* Read from dpfp1 into pair of core regs (w/o clobbering dpfp1)
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* mov_s r3, 0
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* daddh11 r1, r3, r3 ; get "hi" into r1 (dpfp1 unchanged)
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* dexcl1 r0, r1, r3 ; get "low" into r0 (dpfp1 low clobbered)
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* dexcl1 0, r1, r0 ; restore dpfp1 to orig value
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*
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* However we can tweak the read, so that read-out of outgoing task's FPU regs
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* and write of incoming task's regs happen in one shot. So all the work is
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* done before context switch
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*/
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void fpu_save_restore(struct task_struct *prev, struct task_struct *next)
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{
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unsigned int *saveto = &prev->thread.fpu.aux_dpfp[0].l;
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unsigned int *readfrom = &next->thread.fpu.aux_dpfp[0].l;
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const unsigned int zero = 0;
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__asm__ __volatile__(
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"daddh11 %0, %2, %2\n"
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"dexcl1 %1, %3, %4\n"
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: "=&r" (*(saveto + 1)), /* early clobber must here */
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"=&r" (*(saveto))
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: "r" (zero), "r" (*(readfrom + 1)), "r" (*(readfrom))
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);
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__asm__ __volatile__(
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"daddh22 %0, %2, %2\n"
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"dexcl2 %1, %3, %4\n"
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: "=&r"(*(saveto + 3)), /* early clobber must here */
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"=&r"(*(saveto + 2))
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: "r" (zero), "r" (*(readfrom + 3)), "r" (*(readfrom + 2))
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);
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}
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#else
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void fpu_init_task(struct pt_regs *regs)
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{
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const unsigned int fwe = 0x80000000;
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/* default rounding mode */
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write_aux_reg(ARC_REG_FPU_CTRL, 0x100);
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/* Initialize to zero: setting requires FWE be set */
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write_aux_reg(ARC_REG_FPU_STATUS, fwe);
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}
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void fpu_save_restore(struct task_struct *prev, struct task_struct *next)
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{
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struct arc_fpu *save = &prev->thread.fpu;
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struct arc_fpu *restore = &next->thread.fpu;
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const unsigned int fwe = 0x80000000;
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save->ctrl = read_aux_reg(ARC_REG_FPU_CTRL);
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save->status = read_aux_reg(ARC_REG_FPU_STATUS);
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write_aux_reg(ARC_REG_FPU_CTRL, restore->ctrl);
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write_aux_reg(ARC_REG_FPU_STATUS, (fwe | restore->status));
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}
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#endif
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