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c62dfdbbf7
The VCN3 instances can do both decode as well as encode. Share the scheduler load balancing score and remove fixing encode to only the second instance. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
298 lines
10 KiB
C
298 lines
10 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_VCN_H__
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#define __AMDGPU_VCN_H__
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#define AMDGPU_VCN_STACK_SIZE (128*1024)
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#define AMDGPU_VCN_CONTEXT_SIZE (512*1024)
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#define AMDGPU_VCN_FIRMWARE_OFFSET 256
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#define AMDGPU_VCN_MAX_ENC_RINGS 3
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#define AMDGPU_MAX_VCN_INSTANCES 2
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#define AMDGPU_MAX_VCN_ENC_RINGS AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES
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#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
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#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
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#define VCN_DEC_KMD_CMD 0x80000000
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#define VCN_DEC_CMD_FENCE 0x00000000
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#define VCN_DEC_CMD_TRAP 0x00000001
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#define VCN_DEC_CMD_WRITE_REG 0x00000004
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#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
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#define VCN_DEC_CMD_PACKET_START 0x0000000a
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#define VCN_DEC_CMD_PACKET_END 0x0000000b
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#define VCN_DEC_SW_CMD_NO_OP 0x00000000
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#define VCN_DEC_SW_CMD_END 0x00000001
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#define VCN_DEC_SW_CMD_IB 0x00000002
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#define VCN_DEC_SW_CMD_FENCE 0x00000003
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#define VCN_DEC_SW_CMD_TRAP 0x00000004
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#define VCN_DEC_SW_CMD_IB_AUTO 0x00000005
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#define VCN_DEC_SW_CMD_SEMAPHORE 0x00000006
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#define VCN_DEC_SW_CMD_PREEMPT_FENCE 0x00000009
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#define VCN_DEC_SW_CMD_REG_WRITE 0x0000000b
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#define VCN_DEC_SW_CMD_REG_WAIT 0x0000000c
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#define VCN_ENC_CMD_NO_OP 0x00000000
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#define VCN_ENC_CMD_END 0x00000001
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#define VCN_ENC_CMD_IB 0x00000002
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#define VCN_ENC_CMD_FENCE 0x00000003
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#define VCN_ENC_CMD_TRAP 0x00000004
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#define VCN_ENC_CMD_REG_WRITE 0x0000000b
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#define VCN_ENC_CMD_REG_WAIT 0x0000000c
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#define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
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#define VCN1_VID_SOC_ADDRESS_3_0 0x48200
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#define VCN_AON_SOC_ADDRESS_2_0 0x1f800
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#define VCN1_AON_SOC_ADDRESS_3_0 0x48000
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#define VCN_VID_IP_ADDRESS_2_0 0x0
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#define VCN_AON_IP_ADDRESS_2_0 0x30000
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#define mmUVD_RBC_XX_IB_REG_CHECK 0x026b
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#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1
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#define mmUVD_REG_XX_MASK 0x026c
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#define mmUVD_REG_XX_MASK_BASE_IDX 1
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/* 1 second timeout */
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#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
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#define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \
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({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__MASK_EN_MASK | \
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((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
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})
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#define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \
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do { \
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WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
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((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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} while (0)
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#define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \
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({ \
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uint32_t internal_reg_offset, addr; \
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bool video_range, video1_range, aon_range, aon1_range; \
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\
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addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
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addr <<= 2; \
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video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \
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((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \
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video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS_3_0)) && \
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((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS_3_0 + 0x2600))))); \
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aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && \
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((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600))))); \
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aon1_range = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS_3_0)) && \
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((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS_3_0 + 0x600))))); \
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if (video_range) \
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internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + \
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(VCN_VID_IP_ADDRESS_2_0)); \
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else if (aon_range) \
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internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + \
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(VCN_AON_IP_ADDRESS_2_0)); \
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else if (video1_range) \
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internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS_3_0) + \
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(VCN_VID_IP_ADDRESS_2_0)); \
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else if (aon1_range) \
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internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS_3_0) + \
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(VCN_AON_IP_ADDRESS_2_0)); \
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else \
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internal_reg_offset = (0xFFFFF & addr); \
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\
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internal_reg_offset >>= 2; \
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})
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#define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) \
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({ \
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WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
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(0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
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mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
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offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
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})
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#define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \
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do { \
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if (!indirect) { \
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WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
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(0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
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mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
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offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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} else { \
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*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = offset; \
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*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = value; \
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} \
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} while (0)
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#define AMDGPU_VCN_FW_SHARED_FLAG_0_RB (1 << 6)
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#define AMDGPU_VCN_MULTI_QUEUE_FLAG (1 << 8)
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#define AMDGPU_VCN_SW_RING_FLAG (1 << 9)
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#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001
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#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001
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enum fw_queue_mode {
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FW_QUEUE_RING_RESET = 1,
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FW_QUEUE_DPG_HOLD_OFF = 2,
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};
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enum engine_status_constants {
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UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
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UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
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UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 = 0x2A2A8AA0,
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UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
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UVD_STATUS__UVD_BUSY = 0x00000004,
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GB_ADDR_CONFIG_DEFAULT = 0x26010011,
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UVD_STATUS__IDLE = 0x2,
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UVD_STATUS__BUSY = 0x5,
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UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
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UVD_STATUS__RBC_BUSY = 0x1,
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UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
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};
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enum internal_dpg_state {
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VCN_DPG_STATE__UNPAUSE = 0,
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VCN_DPG_STATE__PAUSE,
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};
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struct dpg_pause_state {
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enum internal_dpg_state fw_based;
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enum internal_dpg_state jpeg;
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};
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struct amdgpu_vcn_reg{
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unsigned data0;
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unsigned data1;
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unsigned cmd;
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unsigned nop;
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unsigned context_id;
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unsigned ib_vmid;
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unsigned ib_bar_low;
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unsigned ib_bar_high;
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unsigned ib_size;
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unsigned gp_scratch8;
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unsigned scratch9;
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};
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struct amdgpu_vcn_inst {
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struct amdgpu_bo *vcpu_bo;
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void *cpu_addr;
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uint64_t gpu_addr;
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void *saved_bo;
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struct amdgpu_ring ring_dec;
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struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
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atomic_t sched_score;
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struct amdgpu_irq_src irq;
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struct amdgpu_vcn_reg external;
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struct amdgpu_bo *dpg_sram_bo;
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struct dpg_pause_state pause_state;
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void *dpg_sram_cpu_addr;
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uint64_t dpg_sram_gpu_addr;
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uint32_t *dpg_sram_curr_addr;
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atomic_t dpg_enc_submission_cnt;
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void *fw_shared_cpu_addr;
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uint64_t fw_shared_gpu_addr;
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};
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struct amdgpu_vcn {
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unsigned fw_version;
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struct delayed_work idle_work;
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const struct firmware *fw; /* VCN firmware */
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unsigned num_enc_rings;
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enum amd_powergating_state cur_state;
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bool indirect_sram;
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uint8_t num_vcn_inst;
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struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES];
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struct amdgpu_vcn_reg internal;
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struct mutex vcn_pg_lock;
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struct mutex vcn1_jpeg1_workaround;
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atomic_t total_submission_cnt;
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unsigned harvest_config;
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int (*pause_dpg_mode)(struct amdgpu_device *adev,
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int inst_idx, struct dpg_pause_state *new_state);
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};
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struct amdgpu_fw_shared_rb_ptrs_struct {
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/* to WA DPG R/W ptr issues.*/
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uint32_t rptr;
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uint32_t wptr;
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};
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struct amdgpu_fw_shared_multi_queue {
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uint8_t decode_queue_mode;
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uint8_t encode_generalpurpose_queue_mode;
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uint8_t encode_lowlatency_queue_mode;
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uint8_t encode_realtime_queue_mode;
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uint8_t padding[4];
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};
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struct amdgpu_fw_shared_sw_ring {
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uint8_t is_enabled;
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uint8_t padding[3];
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};
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struct amdgpu_fw_shared {
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uint32_t present_flag_0;
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uint8_t pad[44];
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struct amdgpu_fw_shared_rb_ptrs_struct rb;
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uint8_t pad1[1];
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struct amdgpu_fw_shared_multi_queue multi_queue;
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struct amdgpu_fw_shared_sw_ring sw_ring;
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};
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struct amdgpu_vcn_decode_buffer {
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uint32_t valid_buf_flag;
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uint32_t msg_buffer_address_hi;
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uint32_t msg_buffer_address_lo;
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uint32_t pad[30];
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};
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int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
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int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
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int amdgpu_vcn_suspend(struct amdgpu_device *adev);
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int amdgpu_vcn_resume(struct amdgpu_device *adev);
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void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
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void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
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int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
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int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
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int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
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int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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#endif
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