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![Magnus Damm](/assets/img/avatar_default.png)
Add PFC support for a 32-bit unlock register. Needed to drive the r8a7779 PFC that comes with a funky PMMR register. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
739 lines
16 KiB
C
739 lines
16 KiB
C
/*
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* Pinmuxed GPIO support for SuperH.
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*
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* Copyright (C) 2008 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/bitops.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/ioport.h>
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static void pfc_iounmap(struct pinmux_info *pip)
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{
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int k;
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for (k = 0; k < pip->num_resources; k++)
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if (pip->window[k].virt)
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iounmap(pip->window[k].virt);
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kfree(pip->window);
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pip->window = NULL;
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}
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static int pfc_ioremap(struct pinmux_info *pip)
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{
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struct resource *res;
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int k;
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if (!pip->num_resources)
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return 0;
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pip->window = kzalloc(pip->num_resources * sizeof(*pip->window),
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GFP_NOWAIT);
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if (!pip->window)
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goto err1;
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for (k = 0; k < pip->num_resources; k++) {
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res = pip->resource + k;
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WARN_ON(resource_type(res) != IORESOURCE_MEM);
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pip->window[k].phys = res->start;
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pip->window[k].size = resource_size(res);
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pip->window[k].virt = ioremap_nocache(res->start,
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resource_size(res));
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if (!pip->window[k].virt)
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goto err2;
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}
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return 0;
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err2:
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pfc_iounmap(pip);
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err1:
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return -1;
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}
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static void __iomem *pfc_phys_to_virt(struct pinmux_info *pip,
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unsigned long address)
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{
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struct pfc_window *window;
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int k;
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/* scan through physical windows and convert address */
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for (k = 0; k < pip->num_resources; k++) {
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window = pip->window + k;
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if (address < window->phys)
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continue;
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if (address >= (window->phys + window->size))
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continue;
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return window->virt + (address - window->phys);
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}
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/* no windows defined, register must be 1:1 mapped virt:phys */
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return (void __iomem *)address;
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}
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static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
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{
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if (enum_id < r->begin)
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return 0;
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if (enum_id > r->end)
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return 0;
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return 1;
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}
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static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
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unsigned long reg_width)
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{
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switch (reg_width) {
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case 8:
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return ioread8(mapped_reg);
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case 16:
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return ioread16(mapped_reg);
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case 32:
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return ioread32(mapped_reg);
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}
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BUG();
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return 0;
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}
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static void gpio_write_raw_reg(void __iomem *mapped_reg,
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unsigned long reg_width,
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unsigned long data)
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{
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switch (reg_width) {
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case 8:
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iowrite8(data, mapped_reg);
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return;
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case 16:
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iowrite16(data, mapped_reg);
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return;
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case 32:
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iowrite32(data, mapped_reg);
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return;
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}
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BUG();
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}
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static int gpio_read_bit(struct pinmux_data_reg *dr,
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unsigned long in_pos)
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{
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unsigned long pos;
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pos = dr->reg_width - (in_pos + 1);
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pr_debug("read_bit: addr = %lx, pos = %ld, "
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"r_width = %ld\n", dr->reg, pos, dr->reg_width);
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return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
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}
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static void gpio_write_bit(struct pinmux_data_reg *dr,
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unsigned long in_pos, unsigned long value)
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{
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unsigned long pos;
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pos = dr->reg_width - (in_pos + 1);
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pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
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"r_width = %ld\n",
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dr->reg, !!value, pos, dr->reg_width);
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if (value)
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set_bit(pos, &dr->reg_shadow);
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else
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clear_bit(pos, &dr->reg_shadow);
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gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
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}
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static void config_reg_helper(struct pinmux_info *gpioc,
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struct pinmux_cfg_reg *crp,
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unsigned long in_pos,
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void __iomem **mapped_regp,
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unsigned long *maskp,
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unsigned long *posp)
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{
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int k;
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*mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);
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if (crp->field_width) {
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*maskp = (1 << crp->field_width) - 1;
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*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
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} else {
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*maskp = (1 << crp->var_field_width[in_pos]) - 1;
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*posp = crp->reg_width;
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for (k = 0; k <= in_pos; k++)
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*posp -= crp->var_field_width[k];
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}
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}
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static int read_config_reg(struct pinmux_info *gpioc,
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struct pinmux_cfg_reg *crp,
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unsigned long field)
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{
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void __iomem *mapped_reg;
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unsigned long mask, pos;
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config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
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pr_debug("read_reg: addr = %lx, field = %ld, "
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"r_width = %ld, f_width = %ld\n",
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crp->reg, field, crp->reg_width, crp->field_width);
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return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
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}
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static void write_config_reg(struct pinmux_info *gpioc,
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struct pinmux_cfg_reg *crp,
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unsigned long field, unsigned long value)
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{
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void __iomem *mapped_reg;
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unsigned long mask, pos, data;
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config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
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pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
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"r_width = %ld, f_width = %ld\n",
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crp->reg, value, field, crp->reg_width, crp->field_width);
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mask = ~(mask << pos);
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value = value << pos;
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data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
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data &= mask;
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data |= value;
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if (gpioc->unlock_reg)
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gpio_write_raw_reg(pfc_phys_to_virt(gpioc, gpioc->unlock_reg),
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32, ~data);
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gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
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}
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static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
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{
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struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
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struct pinmux_data_reg *data_reg;
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int k, n;
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if (!enum_in_range(gpiop->enum_id, &gpioc->data))
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return -1;
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k = 0;
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while (1) {
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data_reg = gpioc->data_regs + k;
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if (!data_reg->reg_width)
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break;
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data_reg->mapped_reg = pfc_phys_to_virt(gpioc, data_reg->reg);
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for (n = 0; n < data_reg->reg_width; n++) {
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if (data_reg->enum_ids[n] == gpiop->enum_id) {
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gpiop->flags &= ~PINMUX_FLAG_DREG;
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gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
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gpiop->flags &= ~PINMUX_FLAG_DBIT;
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gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
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return 0;
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}
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}
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k++;
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}
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BUG();
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return -1;
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}
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static void setup_data_regs(struct pinmux_info *gpioc)
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{
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struct pinmux_data_reg *drp;
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int k;
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for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
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setup_data_reg(gpioc, k);
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k = 0;
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while (1) {
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drp = gpioc->data_regs + k;
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if (!drp->reg_width)
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break;
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drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
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drp->reg_width);
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k++;
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}
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}
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static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
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struct pinmux_data_reg **drp, int *bitp)
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{
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struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
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int k, n;
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if (!enum_in_range(gpiop->enum_id, &gpioc->data))
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return -1;
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k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
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n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
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*drp = gpioc->data_regs + k;
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*bitp = n;
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return 0;
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}
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static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
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struct pinmux_cfg_reg **crp,
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int *fieldp, int *valuep,
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unsigned long **cntp)
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{
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struct pinmux_cfg_reg *config_reg;
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unsigned long r_width, f_width, curr_width, ncomb;
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int k, m, n, pos, bit_pos;
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k = 0;
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while (1) {
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config_reg = gpioc->cfg_regs + k;
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r_width = config_reg->reg_width;
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f_width = config_reg->field_width;
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if (!r_width)
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break;
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pos = 0;
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m = 0;
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for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
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if (f_width)
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curr_width = f_width;
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else
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curr_width = config_reg->var_field_width[m];
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ncomb = 1 << curr_width;
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for (n = 0; n < ncomb; n++) {
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if (config_reg->enum_ids[pos + n] == enum_id) {
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*crp = config_reg;
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*fieldp = m;
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*valuep = n;
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*cntp = &config_reg->cnt[m];
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return 0;
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}
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}
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pos += ncomb;
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m++;
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}
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k++;
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}
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return -1;
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}
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static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
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int pos, pinmux_enum_t *enum_idp)
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{
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pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
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pinmux_enum_t *data = gpioc->gpio_data;
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int k;
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if (!enum_in_range(enum_id, &gpioc->data)) {
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if (!enum_in_range(enum_id, &gpioc->mark)) {
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pr_err("non data/mark enum_id for gpio %d\n", gpio);
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return -1;
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}
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}
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if (pos) {
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*enum_idp = data[pos + 1];
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return pos + 1;
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}
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for (k = 0; k < gpioc->gpio_data_size; k++) {
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if (data[k] == enum_id) {
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*enum_idp = data[k + 1];
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return k + 1;
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}
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}
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pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
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return -1;
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}
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enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
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static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
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int pinmux_type, int cfg_mode)
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{
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struct pinmux_cfg_reg *cr = NULL;
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pinmux_enum_t enum_id;
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struct pinmux_range *range;
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int in_range, pos, field, value;
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unsigned long *cntp;
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switch (pinmux_type) {
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case PINMUX_TYPE_FUNCTION:
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range = NULL;
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break;
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case PINMUX_TYPE_OUTPUT:
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range = &gpioc->output;
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break;
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case PINMUX_TYPE_INPUT:
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range = &gpioc->input;
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break;
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case PINMUX_TYPE_INPUT_PULLUP:
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range = &gpioc->input_pu;
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break;
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case PINMUX_TYPE_INPUT_PULLDOWN:
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range = &gpioc->input_pd;
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break;
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default:
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goto out_err;
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}
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pos = 0;
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enum_id = 0;
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field = 0;
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value = 0;
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while (1) {
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pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
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if (pos <= 0)
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goto out_err;
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if (!enum_id)
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break;
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/* first check if this is a function enum */
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in_range = enum_in_range(enum_id, &gpioc->function);
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if (!in_range) {
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/* not a function enum */
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if (range) {
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/*
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* other range exists, so this pin is
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* a regular GPIO pin that now is being
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* bound to a specific direction.
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*
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* for this case we only allow function enums
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* and the enums that match the other range.
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*/
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in_range = enum_in_range(enum_id, range);
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|
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/*
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* special case pass through for fixed
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* input-only or output-only pins without
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* function enum register association.
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*/
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if (in_range && enum_id == range->force)
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continue;
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} else {
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/*
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* no other range exists, so this pin
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* must then be of the function type.
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*
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* allow function type pins to select
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* any combination of function/in/out
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* in their MARK lists.
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*/
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in_range = 1;
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}
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}
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|
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if (!in_range)
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continue;
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if (get_config_reg(gpioc, enum_id, &cr,
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&field, &value, &cntp) != 0)
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goto out_err;
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|
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switch (cfg_mode) {
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case GPIO_CFG_DRYRUN:
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if (!*cntp ||
|
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(read_config_reg(gpioc, cr, field) != value))
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continue;
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break;
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|
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case GPIO_CFG_REQ:
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write_config_reg(gpioc, cr, field, value);
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*cntp = *cntp + 1;
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break;
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|
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case GPIO_CFG_FREE:
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*cntp = *cntp - 1;
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break;
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}
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}
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|
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return 0;
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out_err:
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return -1;
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}
|
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|
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static DEFINE_SPINLOCK(gpio_lock);
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|
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static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
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{
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return container_of(chip, struct pinmux_info, chip);
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}
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|
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static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
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|
{
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struct pinmux_info *gpioc = chip_to_pinmux(chip);
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struct pinmux_data_reg *dummy;
|
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unsigned long flags;
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int i, ret, pinmux_type;
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ret = -EINVAL;
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|
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if (!gpioc)
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goto err_out;
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spin_lock_irqsave(&gpio_lock, flags);
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|
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if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
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goto err_unlock;
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|
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/* setup pin function here if no data is associated with pin */
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|
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if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
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pinmux_type = PINMUX_TYPE_FUNCTION;
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else
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pinmux_type = PINMUX_TYPE_GPIO;
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|
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if (pinmux_type == PINMUX_TYPE_FUNCTION) {
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if (pinmux_config_gpio(gpioc, offset,
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pinmux_type,
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GPIO_CFG_DRYRUN) != 0)
|
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goto err_unlock;
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|
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if (pinmux_config_gpio(gpioc, offset,
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pinmux_type,
|
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GPIO_CFG_REQ) != 0)
|
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BUG();
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}
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|
|
gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
|
|
gpioc->gpios[offset].flags |= pinmux_type;
|
|
|
|
ret = 0;
|
|
err_unlock:
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
err_out:
|
|
return ret;
|
|
}
|
|
|
|
static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct pinmux_info *gpioc = chip_to_pinmux(chip);
|
|
unsigned long flags;
|
|
int pinmux_type;
|
|
|
|
if (!gpioc)
|
|
return;
|
|
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
|
|
pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
|
|
pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
|
|
gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
|
|
gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
|
|
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
}
|
|
|
|
static int pinmux_direction(struct pinmux_info *gpioc,
|
|
unsigned gpio, int new_pinmux_type)
|
|
{
|
|
int pinmux_type;
|
|
int ret = -EINVAL;
|
|
|
|
if (!gpioc)
|
|
goto err_out;
|
|
|
|
pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
|
|
|
|
switch (pinmux_type) {
|
|
case PINMUX_TYPE_GPIO:
|
|
break;
|
|
case PINMUX_TYPE_OUTPUT:
|
|
case PINMUX_TYPE_INPUT:
|
|
case PINMUX_TYPE_INPUT_PULLUP:
|
|
case PINMUX_TYPE_INPUT_PULLDOWN:
|
|
pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
|
|
break;
|
|
default:
|
|
goto err_out;
|
|
}
|
|
|
|
if (pinmux_config_gpio(gpioc, gpio,
|
|
new_pinmux_type,
|
|
GPIO_CFG_DRYRUN) != 0)
|
|
goto err_out;
|
|
|
|
if (pinmux_config_gpio(gpioc, gpio,
|
|
new_pinmux_type,
|
|
GPIO_CFG_REQ) != 0)
|
|
BUG();
|
|
|
|
gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
|
|
gpioc->gpios[gpio].flags |= new_pinmux_type;
|
|
|
|
ret = 0;
|
|
err_out:
|
|
return ret;
|
|
}
|
|
|
|
static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct pinmux_info *gpioc = chip_to_pinmux(chip);
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void sh_gpio_set_value(struct pinmux_info *gpioc,
|
|
unsigned gpio, int value)
|
|
{
|
|
struct pinmux_data_reg *dr = NULL;
|
|
int bit = 0;
|
|
|
|
if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
|
|
BUG();
|
|
else
|
|
gpio_write_bit(dr, bit, value);
|
|
}
|
|
|
|
static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
|
|
int value)
|
|
{
|
|
struct pinmux_info *gpioc = chip_to_pinmux(chip);
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
sh_gpio_set_value(gpioc, offset, value);
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
|
|
{
|
|
struct pinmux_data_reg *dr = NULL;
|
|
int bit = 0;
|
|
|
|
if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
|
|
return -EINVAL;
|
|
|
|
return gpio_read_bit(dr, bit);
|
|
}
|
|
|
|
static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
return sh_gpio_get_value(chip_to_pinmux(chip), offset);
|
|
}
|
|
|
|
static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
|
{
|
|
sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
|
|
}
|
|
|
|
static int sh_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct pinmux_info *gpioc = chip_to_pinmux(chip);
|
|
pinmux_enum_t enum_id;
|
|
pinmux_enum_t *enum_ids;
|
|
int i, k, pos;
|
|
|
|
pos = 0;
|
|
enum_id = 0;
|
|
while (1) {
|
|
pos = get_gpio_enum_id(gpioc, offset, pos, &enum_id);
|
|
if (pos <= 0 || !enum_id)
|
|
break;
|
|
|
|
for (i = 0; i < gpioc->gpio_irq_size; i++) {
|
|
enum_ids = gpioc->gpio_irq[i].enum_ids;
|
|
for (k = 0; enum_ids[k]; k++) {
|
|
if (enum_ids[k] == enum_id)
|
|
return gpioc->gpio_irq[i].irq;
|
|
}
|
|
}
|
|
}
|
|
|
|
return -ENOSYS;
|
|
}
|
|
|
|
int register_pinmux(struct pinmux_info *pip)
|
|
{
|
|
struct gpio_chip *chip = &pip->chip;
|
|
int ret;
|
|
|
|
pr_info("%s handling gpio %d -> %d\n",
|
|
pip->name, pip->first_gpio, pip->last_gpio);
|
|
|
|
ret = pfc_ioremap(pip);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
setup_data_regs(pip);
|
|
|
|
chip->request = sh_gpio_request;
|
|
chip->free = sh_gpio_free;
|
|
chip->direction_input = sh_gpio_direction_input;
|
|
chip->get = sh_gpio_get;
|
|
chip->direction_output = sh_gpio_direction_output;
|
|
chip->set = sh_gpio_set;
|
|
chip->to_irq = sh_gpio_to_irq;
|
|
|
|
WARN_ON(pip->first_gpio != 0); /* needs testing */
|
|
|
|
chip->label = pip->name;
|
|
chip->owner = THIS_MODULE;
|
|
chip->base = pip->first_gpio;
|
|
chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
|
|
|
|
ret = gpiochip_add(chip);
|
|
if (ret < 0)
|
|
pfc_iounmap(pip);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int unregister_pinmux(struct pinmux_info *pip)
|
|
{
|
|
pr_info("%s deregistering\n", pip->name);
|
|
pfc_iounmap(pip);
|
|
return gpiochip_remove(&pip->chip);
|
|
}
|