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f36bbf21e8
Rewrite clear_user() on the same principle as memset(0), making use
of dcbz to clear complete cache lines.
This code is a copy/paste of memset(), with some modifications
in order to retrieve remaining number of bytes to be cleared,
as it needs to be returned in case of error.
On the same way as done on PPC64 in commit 17968fbbd1
("powerpc: 64bit optimised __clear_user"), the patch moves
__clear_user() into a dedicated file string_32.S
On a MPC885, throughput is almost doubled:
Before:
~# dd if=/dev/zero of=/dev/null bs=1M count=1000
1048576000 bytes (1000.0MB) copied, 18.990779 seconds, 52.7MB/s
After:
~# dd if=/dev/zero of=/dev/null bs=1M count=1000
1048576000 bytes (1000.0MB) copied, 9.611468 seconds, 104.0MB/s
On a MPC8321, throughput is multiplied by 2.12:
Before:
root@vgoippro:~# dd if=/dev/zero of=/dev/null bs=1M count=1000
1048576000 bytes (1000.0MB) copied, 6.844352 seconds, 146.1MB/s
After:
root@vgoippro:~# dd if=/dev/zero of=/dev/null bs=1M count=1000
1048576000 bytes (1000.0MB) copied, 3.218854 seconds, 310.7MB/s
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
90 lines
1.4 KiB
ArmAsm
90 lines
1.4 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* String handling functions for PowerPC32
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*
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* Copyright (C) 1996 Paul Mackerras.
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*
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*/
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#include <asm/ppc_asm.h>
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#include <asm/export.h>
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#include <asm/cache.h>
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.text
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CACHELINE_BYTES = L1_CACHE_BYTES
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LG_CACHELINE_BYTES = L1_CACHE_SHIFT
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CACHELINE_MASK = (L1_CACHE_BYTES-1)
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_GLOBAL(__clear_user)
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/*
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* Use dcbz on the complete cache lines in the destination
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* to set them to zero. This requires that the destination
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* area is cacheable.
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*/
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cmplwi cr0, r4, 4
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mr r10, r3
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li r3, 0
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blt 7f
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11: stw r3, 0(r10)
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beqlr
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andi. r0, r10, 3
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add r11, r0, r4
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subf r6, r0, r10
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clrlwi r7, r6, 32 - LG_CACHELINE_BYTES
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add r8, r7, r11
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srwi r9, r8, LG_CACHELINE_BYTES
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addic. r9, r9, -1 /* total number of complete cachelines */
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ble 2f
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xori r0, r7, CACHELINE_MASK & ~3
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srwi. r0, r0, 2
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beq 3f
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mtctr r0
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4: stwu r3, 4(r6)
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bdnz 4b
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3: mtctr r9
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li r7, 4
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10: dcbz r7, r6
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addi r6, r6, CACHELINE_BYTES
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bdnz 10b
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clrlwi r11, r8, 32 - LG_CACHELINE_BYTES
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addi r11, r11, 4
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2: srwi r0 ,r11 ,2
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mtctr r0
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bdz 6f
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1: stwu r3, 4(r6)
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bdnz 1b
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6: andi. r11, r11, 3
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beqlr
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mtctr r11
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addi r6, r6, 3
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8: stbu r3, 1(r6)
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bdnz 8b
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blr
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7: cmpwi cr0, r4, 0
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beqlr
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mtctr r4
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addi r6, r10, -1
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9: stbu r3, 1(r6)
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bdnz 9b
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blr
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90: mr r3, r4
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blr
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91: add r3, r10, r4
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subf r3, r6, r3
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blr
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EX_TABLE(11b, 90b)
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EX_TABLE(4b, 91b)
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EX_TABLE(10b, 91b)
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EX_TABLE(1b, 91b)
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EX_TABLE(8b, 91b)
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EX_TABLE(9b, 91b)
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EXPORT_SYMBOL(__clear_user)
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