474 lines
11 KiB
Plaintext
474 lines
11 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* GS101 SoC
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*
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* Copyright 2019-2023 Google LLC
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* Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
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*/
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#include <dt-bindings/clock/google,gs101.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/samsung,exynos-usi.h>
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/ {
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compatible = "google,gs101";
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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pinctrl0 = &pinctrl_gpio_alive;
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pinctrl1 = &pinctrl_far_alive;
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pinctrl2 = &pinctrl_gsacore;
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pinctrl3 = &pinctrl_gsactrl;
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pinctrl4 = &pinctrl_peric0;
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pinctrl5 = &pinctrl_peric1;
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pinctrl6 = &pinctrl_hsi1;
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pinctrl7 = &pinctrl_hsi2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&cpu6>;
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};
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core1 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0000>;
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enable-method = "psci";
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cpu-idle-states = <&ANANKE_CPU_SLEEP>;
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capacity-dmips-mhz = <250>;
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dynamic-power-coefficient = <70>;
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0100>;
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enable-method = "psci";
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cpu-idle-states = <&ANANKE_CPU_SLEEP>;
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capacity-dmips-mhz = <250>;
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dynamic-power-coefficient = <70>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0200>;
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enable-method = "psci";
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cpu-idle-states = <&ANANKE_CPU_SLEEP>;
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capacity-dmips-mhz = <250>;
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dynamic-power-coefficient = <70>;
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0300>;
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enable-method = "psci";
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cpu-idle-states = <&ANANKE_CPU_SLEEP>;
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capacity-dmips-mhz = <250>;
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dynamic-power-coefficient = <70>;
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};
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cpu4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0400>;
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enable-method = "psci";
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cpu-idle-states = <&ENYO_CPU_SLEEP>;
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capacity-dmips-mhz = <620>;
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dynamic-power-coefficient = <284>;
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};
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cpu5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0500>;
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enable-method = "psci";
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cpu-idle-states = <&ENYO_CPU_SLEEP>;
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capacity-dmips-mhz = <620>;
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dynamic-power-coefficient = <284>;
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};
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cpu6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-x1";
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reg = <0x0600>;
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enable-method = "psci";
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cpu-idle-states = <&HERA_CPU_SLEEP>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <650>;
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};
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cpu7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-x1";
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reg = <0x0700>;
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enable-method = "psci";
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cpu-idle-states = <&HERA_CPU_SLEEP>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <650>;
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};
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idle-states {
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entry-method = "psci";
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ANANKE_CPU_SLEEP: cpu-ananke-sleep {
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idle-state-name = "c2";
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <70>;
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exit-latency-us = <160>;
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min-residency-us = <2000>;
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};
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ENYO_CPU_SLEEP: cpu-enyo-sleep {
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idle-state-name = "c2";
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <150>;
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exit-latency-us = <190>;
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min-residency-us = <2500>;
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};
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HERA_CPU_SLEEP: cpu-hera-sleep {
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idle-state-name = "c2";
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <235>;
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exit-latency-us = <220>;
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min-residency-us = <3500>;
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};
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};
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};
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/* TODO replace with CCF clock */
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dummy_clk: clock-3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12345>;
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clock-output-names = "pclk";
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};
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/* ect node is required to be present by bootloader */
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ect {
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};
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ext_24_5m: clock-1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "oscclk";
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};
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ext_200m: clock-2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "ext-200m";
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};
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pmu-0 {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
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};
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pmu-1 {
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compatible = "arm,cortex-a76-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
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};
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pmu-2 {
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compatible = "arm,cortex-x1-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>;
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};
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pmu-3 {
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compatible = "arm,dsu-pmu";
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interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>;
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cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
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<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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gsa_reserved_protected: gsa@90200000 {
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reg = <0x0 0x90200000 0x400000>;
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no-map;
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};
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tpu_fw_reserved: tpu-fw@93000000 {
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reg = <0x0 0x93000000 0x1000000>;
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no-map;
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};
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aoc_reserve: aoc@94000000 {
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reg = <0x0 0x94000000 0x03000000>;
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no-map;
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};
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abl_reserved: abl@f8800000 {
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reg = <0x0 0xf8800000 0x02000000>;
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no-map;
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};
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dss_log_reserved: dss-log-reserved@fd3f0000 {
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reg = <0x0 0xfd3f0000 0x0000e000>;
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no-map;
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};
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debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 {
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reg = <0x0 0xfd3fe000 0x00001000>;
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no-map;
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};
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bldr_log_reserved: bldr-log-reserved@fd800000 {
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reg = <0x0 0xfd800000 0x00100000>;
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no-map;
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};
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bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 {
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reg = <0x0 0xfd900000 0x00002000>;
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no-map;
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};
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};
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soc: soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x40000000>;
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cmu_misc: clock-controller@10010000 {
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compatible = "google,gs101-cmu-misc";
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reg = <0x10010000 0x8000>;
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#clock-cells = <1>;
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clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
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<&cmu_top CLK_DOUT_CMU_MISC_SSS>;
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clock-names = "bus", "sss";
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};
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watchdog_cl0: watchdog@10060000 {
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compatible = "google,gs101-wdt";
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reg = <0x10060000 0x100>;
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interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>,
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<&ext_24_5m>;
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clock-names = "watchdog", "watchdog_src";
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samsung,syscon-phandle = <&pmu_system_controller>;
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samsung,cluster-index = <0>;
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status = "disabled";
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};
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watchdog_cl1: watchdog@10070000 {
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compatible = "google,gs101-wdt";
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reg = <0x10070000 0x100>;
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interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>,
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<&ext_24_5m>;
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clock-names = "watchdog", "watchdog_src";
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samsung,syscon-phandle = <&pmu_system_controller>;
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samsung,cluster-index = <1>;
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status = "disabled";
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};
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gic: interrupt-controller@10400000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <4>;
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interrupt-controller;
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reg = <0x10400000 0x10000>, /* GICD */
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<0x10440000 0x100000>;/* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
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ppi-partitions {
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ppi_cluster0: interrupt-partition-0 {
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affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
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};
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ppi_cluster1: interrupt-partition-1 {
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affinity = <&cpu4 &cpu5>;
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};
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ppi_cluster2: interrupt-partition-2 {
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affinity = <&cpu6 &cpu7>;
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};
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};
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};
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sysreg_peric0: syscon@10820000 {
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compatible = "google,gs101-peric0-sysreg", "syscon";
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reg = <0x10820000 0x10000>;
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};
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pinctrl_peric0: pinctrl@10840000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x10840000 0x00001000>;
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interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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usi_uart: usi@10a000c0 {
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compatible = "google,gs101-usi",
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"samsung,exynos850-usi";
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reg = <0x10a000c0 0x20>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&dummy_clk>, <&dummy_clk>;
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clock-names = "pclk", "ipclk";
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samsung,sysreg = <&sysreg_peric0 0x1020>;
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samsung,mode = <USI_V2_UART>;
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status = "disabled";
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serial_0: serial@10a00000 {
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compatible = "google,gs101-uart";
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reg = <0x10a00000 0xc0>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 634
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IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&dummy_clk 0>, <&dummy_clk 0>;
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clock-names = "uart", "clk_uart_baud0";
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samsung,uart-fifosize = <256>;
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status = "disabled";
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};
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};
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sysreg_peric1: syscon@10c20000 {
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compatible = "google,gs101-peric1-sysreg", "syscon";
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reg = <0x10c20000 0x10000>;
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};
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pinctrl_peric1: pinctrl@10c40000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x10c40000 0x00001000>;
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interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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pinctrl_hsi1: pinctrl@11840000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x11840000 0x00001000>;
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interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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pinctrl_hsi2: pinctrl@14440000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x14440000 0x00001000>;
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interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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cmu_apm: clock-controller@17400000 {
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compatible = "google,gs101-cmu-apm";
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reg = <0x17400000 0x8000>;
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#clock-cells = <1>;
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clocks = <&ext_24_5m>;
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clock-names = "oscclk";
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};
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sysreg_apm: syscon@174204e0 {
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compatible = "google,gs101-apm-sysreg", "syscon";
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reg = <0x174204e0 0x1000>;
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};
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pmu_system_controller: system-controller@17460000 {
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compatible = "google,gs101-pmu", "syscon";
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reg = <0x17460000 0x10000>;
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};
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pinctrl_gpio_alive: pinctrl@174d0000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x174d0000 0x00001000>;
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wakeup-interrupt-controller {
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compatible = "google,gs101-wakeup-eint",
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"samsung,exynos850-wakeup-eint",
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"samsung,exynos7-wakeup-eint";
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};
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};
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pinctrl_far_alive: pinctrl@174e0000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x174e0000 0x00001000>;
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wakeup-interrupt-controller {
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compatible = "google,gs101-wakeup-eint",
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"samsung,exynos850-wakeup-eint",
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"samsung,exynos7-wakeup-eint";
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};
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};
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pinctrl_gsactrl: pinctrl@17940000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x17940000 0x00001000>;
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};
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pinctrl_gsacore: pinctrl@17a80000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x17a80000 0x00001000>;
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};
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cmu_top: clock-controller@1e080000 {
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compatible = "google,gs101-cmu-top";
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reg = <0x1e080000 0x8000>;
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#clock-cells = <1>;
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clocks = <&ext_24_5m>;
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clock-names = "oscclk";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts =
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<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
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};
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};
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#include "gs101-pinctrl.dtsi"
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