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![Jon Hunter](/assets/img/avatar_default.png)
The firmware parameter that contains the IRQ sense bits may also contain other data. When return the IRQ type, bits outside of these sense bits should be masked. If these bits are not masked and irq_create_fwspec_mapping() is called to map an IRQ, then the comparison of the type returned from irq_domain_translate() will never match that returned by irq_get_trigger_type() (because this function masks the none sense bits) and so we will always call irq_set_irq_type() to program the type even if it was not really necessary. Currently, the downside to this is unnecessarily re-programmming the type but nevertheless this should be avoided. The Tegra LIC and TI Crossbar irqchips all have client instances (from reviewing the device-tree sources) where bits outside the IRQ sense bits are set, but do not mask these bits. Therefore, ensure these bits are masked for these irqchips. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
369 lines
8.4 KiB
C
369 lines
8.4 KiB
C
/*
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* drivers/irqchip/irq-crossbar.c
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
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* Author: Sricharan R <r.sricharan@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#define IRQ_FREE -1
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#define IRQ_RESERVED -2
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#define IRQ_SKIP -3
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#define GIC_IRQ_START 32
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/**
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* struct crossbar_device - crossbar device description
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* @lock: spinlock serializing access to @irq_map
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* @int_max: maximum number of supported interrupts
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* @safe_map: safe default value to initialize the crossbar
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* @max_crossbar_sources: Maximum number of crossbar sources
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* @irq_map: array of interrupts to crossbar number mapping
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* @crossbar_base: crossbar base address
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* @register_offsets: offsets for each irq number
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* @write: register write function pointer
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*/
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struct crossbar_device {
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raw_spinlock_t lock;
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uint int_max;
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uint safe_map;
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uint max_crossbar_sources;
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uint *irq_map;
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void __iomem *crossbar_base;
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int *register_offsets;
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void (*write)(int, int);
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};
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static struct crossbar_device *cb;
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static void crossbar_writel(int irq_no, int cb_no)
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{
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writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static void crossbar_writew(int irq_no, int cb_no)
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{
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writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static void crossbar_writeb(int irq_no, int cb_no)
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{
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writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static struct irq_chip crossbar_chip = {
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.name = "CBAR",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_type = irq_chip_set_type_parent,
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.flags = IRQCHIP_MASK_ON_SUSPEND |
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IRQCHIP_SKIP_SET_WAKE,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
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irq_hw_number_t hwirq)
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{
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struct irq_fwspec fwspec;
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int i;
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int err;
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if (!irq_domain_get_of_node(domain->parent))
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return -EINVAL;
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raw_spin_lock(&cb->lock);
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for (i = cb->int_max - 1; i >= 0; i--) {
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if (cb->irq_map[i] == IRQ_FREE) {
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cb->irq_map[i] = hwirq;
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break;
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}
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}
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raw_spin_unlock(&cb->lock);
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if (i < 0)
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return -ENODEV;
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 3;
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fwspec.param[0] = 0; /* SPI */
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fwspec.param[1] = i;
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fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
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err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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if (err)
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cb->irq_map[i] = IRQ_FREE;
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else
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cb->write(i, hwirq);
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return err;
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}
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static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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irq_hw_number_t hwirq;
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int i;
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if (fwspec->param_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (fwspec->param[0] != 0)
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return -EINVAL; /* No PPI should point to this domain */
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hwirq = fwspec->param[1];
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if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
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return -EINVAL; /* Can't deal with this */
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for (i = 0; i < nr_irqs; i++) {
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int err = allocate_gic_irq(d, virq + i, hwirq + i);
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if (err)
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return err;
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irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
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&crossbar_chip, NULL);
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}
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return 0;
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}
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/**
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* crossbar_domain_free - unmap/free a crossbar<->irq connection
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* @domain: domain of irq to unmap
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* @virq: virq number
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* @nr_irqs: number of irqs to free
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*
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* We do not maintain a use count of total number of map/unmap
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* calls for a particular irq to find out if a irq can be really
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* unmapped. This is because unmap is called during irq_dispose_mapping(irq),
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* after which irq is anyways unusable. So an explicit map has to be called
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* after that.
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*/
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static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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int i;
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raw_spin_lock(&cb->lock);
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for (i = 0; i < nr_irqs; i++) {
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struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
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irq_domain_reset_irq_data(d);
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cb->irq_map[d->hwirq] = IRQ_FREE;
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cb->write(d->hwirq, cb->safe_map);
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}
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raw_spin_unlock(&cb->lock);
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}
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static int crossbar_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0] != 0)
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return -EINVAL;
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*hwirq = fwspec->param[1];
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*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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return -EINVAL;
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}
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static const struct irq_domain_ops crossbar_domain_ops = {
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.alloc = crossbar_domain_alloc,
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.free = crossbar_domain_free,
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.translate = crossbar_domain_translate,
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};
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static int __init crossbar_of_init(struct device_node *node)
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{
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int i, size, max = 0, reserved = 0, entry;
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const __be32 *irqsr;
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int ret = -ENOMEM;
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cb = kzalloc(sizeof(*cb), GFP_KERNEL);
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if (!cb)
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return ret;
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cb->crossbar_base = of_iomap(node, 0);
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if (!cb->crossbar_base)
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goto err_cb;
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of_property_read_u32(node, "ti,max-crossbar-sources",
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&cb->max_crossbar_sources);
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if (!cb->max_crossbar_sources) {
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pr_err("missing 'ti,max-crossbar-sources' property\n");
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ret = -EINVAL;
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goto err_base;
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}
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of_property_read_u32(node, "ti,max-irqs", &max);
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if (!max) {
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pr_err("missing 'ti,max-irqs' property\n");
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ret = -EINVAL;
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goto err_base;
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}
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cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
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if (!cb->irq_map)
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goto err_base;
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cb->int_max = max;
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for (i = 0; i < max; i++)
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cb->irq_map[i] = IRQ_FREE;
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/* Get and mark reserved irqs */
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irqsr = of_get_property(node, "ti,irqs-reserved", &size);
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if (irqsr) {
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size /= sizeof(__be32);
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for (i = 0; i < size; i++) {
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of_property_read_u32_index(node,
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"ti,irqs-reserved",
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i, &entry);
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if (entry >= max) {
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pr_err("Invalid reserved entry\n");
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ret = -EINVAL;
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goto err_irq_map;
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}
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cb->irq_map[entry] = IRQ_RESERVED;
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}
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}
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/* Skip irqs hardwired to bypass the crossbar */
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irqsr = of_get_property(node, "ti,irqs-skip", &size);
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if (irqsr) {
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size /= sizeof(__be32);
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for (i = 0; i < size; i++) {
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of_property_read_u32_index(node,
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"ti,irqs-skip",
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i, &entry);
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if (entry >= max) {
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pr_err("Invalid skip entry\n");
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ret = -EINVAL;
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goto err_irq_map;
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}
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cb->irq_map[entry] = IRQ_SKIP;
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}
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}
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cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
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if (!cb->register_offsets)
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goto err_irq_map;
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of_property_read_u32(node, "ti,reg-size", &size);
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switch (size) {
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case 1:
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cb->write = crossbar_writeb;
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break;
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case 2:
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cb->write = crossbar_writew;
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break;
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case 4:
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cb->write = crossbar_writel;
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break;
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default:
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pr_err("Invalid reg-size property\n");
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ret = -EINVAL;
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goto err_reg_offset;
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break;
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}
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/*
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* Register offsets are not linear because of the
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* reserved irqs. so find and store the offsets once.
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*/
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for (i = 0; i < max; i++) {
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if (cb->irq_map[i] == IRQ_RESERVED)
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continue;
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cb->register_offsets[i] = reserved;
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reserved += size;
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}
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of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
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/* Initialize the crossbar with safe map to start with */
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for (i = 0; i < max; i++) {
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if (cb->irq_map[i] == IRQ_RESERVED ||
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cb->irq_map[i] == IRQ_SKIP)
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continue;
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cb->write(i, cb->safe_map);
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}
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raw_spin_lock_init(&cb->lock);
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return 0;
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err_reg_offset:
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kfree(cb->register_offsets);
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err_irq_map:
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kfree(cb->irq_map);
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err_base:
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iounmap(cb->crossbar_base);
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err_cb:
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kfree(cb);
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cb = NULL;
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return ret;
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}
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static int __init irqcrossbar_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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int err;
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if (!parent) {
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pr_err("%s: no parent, giving up\n", node->full_name);
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return -ENODEV;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%s: unable to obtain parent domain\n", node->full_name);
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return -ENXIO;
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}
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err = crossbar_of_init(node);
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if (err)
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return err;
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domain = irq_domain_add_hierarchy(parent_domain, 0,
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cb->max_crossbar_sources,
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node, &crossbar_domain_ops,
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NULL);
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if (!domain) {
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pr_err("%s: failed to allocated domain\n", node->full_name);
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return -ENOMEM;
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}
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return 0;
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}
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IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);
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