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![Fabio Estevam](/assets/img/avatar_default.png)
PTR_ERR should access the value just tested by IS_ERR. The semantic patch that makes this change is available in scripts/coccinelle/tests/odd_ptr_err.cocci. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
976 lines
24 KiB
C
976 lines
24 KiB
C
/*
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* Driver for Cirrus Logic EP93xx SPI controller.
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*
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* Copyright (C) 2010-2011 Mika Westerberg
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*
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* Explicit FIFO handling code was inspired by amba-pl022 driver.
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*
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* Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
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*
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* For more information about the SPI controller see documentation on Cirrus
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* Logic web site:
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* http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/scatterlist.h>
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#include <linux/spi/spi.h>
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#include <linux/platform_data/dma-ep93xx.h>
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#include <linux/platform_data/spi-ep93xx.h>
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#define SSPCR0 0x0000
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#define SSPCR0_MODE_SHIFT 6
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#define SSPCR0_SCR_SHIFT 8
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#define SSPCR1 0x0004
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#define SSPCR1_RIE BIT(0)
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#define SSPCR1_TIE BIT(1)
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#define SSPCR1_RORIE BIT(2)
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#define SSPCR1_LBM BIT(3)
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#define SSPCR1_SSE BIT(4)
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#define SSPCR1_MS BIT(5)
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#define SSPCR1_SOD BIT(6)
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#define SSPDR 0x0008
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#define SSPSR 0x000c
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#define SSPSR_TFE BIT(0)
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#define SSPSR_TNF BIT(1)
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#define SSPSR_RNE BIT(2)
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#define SSPSR_RFF BIT(3)
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#define SSPSR_BSY BIT(4)
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#define SSPCPSR 0x0010
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#define SSPIIR 0x0014
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#define SSPIIR_RIS BIT(0)
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#define SSPIIR_TIS BIT(1)
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#define SSPIIR_RORIS BIT(2)
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#define SSPICR SSPIIR
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/* timeout in milliseconds */
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#define SPI_TIMEOUT 5
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/* maximum depth of RX/TX FIFO */
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#define SPI_FIFO_SIZE 8
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/**
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* struct ep93xx_spi - EP93xx SPI controller structure
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* @pdev: pointer to platform device
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* @clk: clock for the controller
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* @regs_base: pointer to ioremap()'d registers
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* @sspdr_phys: physical address of the SSPDR register
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* @wait: wait here until given transfer is completed
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* @current_msg: message that is currently processed (or %NULL if none)
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* @tx: current byte in transfer to transmit
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* @rx: current byte in transfer to receive
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* @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
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* frame decreases this level and sending one frame increases it.
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* @dma_rx: RX DMA channel
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* @dma_tx: TX DMA channel
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* @dma_rx_data: RX parameters passed to the DMA engine
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* @dma_tx_data: TX parameters passed to the DMA engine
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* @rx_sgt: sg table for RX transfers
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* @tx_sgt: sg table for TX transfers
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* @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
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* the client
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*/
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struct ep93xx_spi {
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const struct platform_device *pdev;
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struct clk *clk;
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void __iomem *regs_base;
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unsigned long sspdr_phys;
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struct completion wait;
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struct spi_message *current_msg;
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size_t tx;
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size_t rx;
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size_t fifo_level;
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struct dma_chan *dma_rx;
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struct dma_chan *dma_tx;
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struct ep93xx_dma_data dma_rx_data;
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struct ep93xx_dma_data dma_tx_data;
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struct sg_table rx_sgt;
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struct sg_table tx_sgt;
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void *zeropage;
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};
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/**
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* struct ep93xx_spi_chip - SPI device hardware settings
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* @spi: back pointer to the SPI device
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* @ops: private chip operations
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*/
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struct ep93xx_spi_chip {
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const struct spi_device *spi;
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struct ep93xx_spi_chip_ops *ops;
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};
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/* converts bits per word to CR0.DSS value */
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#define bits_per_word_to_dss(bpw) ((bpw) - 1)
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static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi,
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u16 reg, u8 value)
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{
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writeb(value, espi->regs_base + reg);
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}
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static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
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{
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return readb(spi->regs_base + reg);
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}
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static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi,
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u16 reg, u16 value)
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{
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writew(value, espi->regs_base + reg);
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}
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static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
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{
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return readw(spi->regs_base + reg);
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}
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static int ep93xx_spi_enable(const struct ep93xx_spi *espi)
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{
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u8 regval;
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int err;
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err = clk_enable(espi->clk);
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if (err)
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return err;
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regval = ep93xx_spi_read_u8(espi, SSPCR1);
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regval |= SSPCR1_SSE;
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ep93xx_spi_write_u8(espi, SSPCR1, regval);
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return 0;
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}
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static void ep93xx_spi_disable(const struct ep93xx_spi *espi)
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{
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u8 regval;
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regval = ep93xx_spi_read_u8(espi, SSPCR1);
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regval &= ~SSPCR1_SSE;
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ep93xx_spi_write_u8(espi, SSPCR1, regval);
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clk_disable(espi->clk);
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}
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static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
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{
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u8 regval;
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regval = ep93xx_spi_read_u8(espi, SSPCR1);
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regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
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ep93xx_spi_write_u8(espi, SSPCR1, regval);
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}
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static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
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{
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u8 regval;
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regval = ep93xx_spi_read_u8(espi, SSPCR1);
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regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
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ep93xx_spi_write_u8(espi, SSPCR1, regval);
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}
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/**
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* ep93xx_spi_calc_divisors() - calculates SPI clock divisors
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* @espi: ep93xx SPI controller struct
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* @rate: desired SPI output clock rate
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* @div_cpsr: pointer to return the cpsr (pre-scaler) divider
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* @div_scr: pointer to return the scr divider
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*/
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static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
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u32 rate, u8 *div_cpsr, u8 *div_scr)
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{
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struct spi_master *master = platform_get_drvdata(espi->pdev);
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unsigned long spi_clk_rate = clk_get_rate(espi->clk);
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int cpsr, scr;
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/*
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* Make sure that max value is between values supported by the
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* controller. Note that minimum value is already checked in
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* ep93xx_spi_transfer_one_message().
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*/
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rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
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/*
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* Calculate divisors so that we can get speed according the
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* following formula:
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* rate = spi_clock_rate / (cpsr * (1 + scr))
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*
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* cpsr must be even number and starts from 2, scr can be any number
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* between 0 and 255.
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*/
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for (cpsr = 2; cpsr <= 254; cpsr += 2) {
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for (scr = 0; scr <= 255; scr++) {
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if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
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*div_scr = (u8)scr;
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*div_cpsr = (u8)cpsr;
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return 0;
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}
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}
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}
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return -EINVAL;
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}
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static void ep93xx_spi_cs_control(struct spi_device *spi, bool control)
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{
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struct ep93xx_spi_chip *chip = spi_get_ctldata(spi);
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int value = (spi->mode & SPI_CS_HIGH) ? control : !control;
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if (chip->ops && chip->ops->cs_control)
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chip->ops->cs_control(spi, value);
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}
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/**
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* ep93xx_spi_setup() - setup an SPI device
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* @spi: SPI device to setup
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*
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* This function sets up SPI device mode, speed etc. Can be called multiple
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* times for a single device. Returns %0 in case of success, negative error in
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* case of failure. When this function returns success, the device is
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* deselected.
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*/
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static int ep93xx_spi_setup(struct spi_device *spi)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
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struct ep93xx_spi_chip *chip;
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chip = spi_get_ctldata(spi);
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if (!chip) {
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dev_dbg(&espi->pdev->dev, "initial setup for %s\n",
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spi->modalias);
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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chip->spi = spi;
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chip->ops = spi->controller_data;
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if (chip->ops && chip->ops->setup) {
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int ret = chip->ops->setup(spi);
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if (ret) {
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kfree(chip);
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return ret;
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}
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}
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spi_set_ctldata(spi, chip);
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}
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ep93xx_spi_cs_control(spi, false);
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return 0;
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}
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/**
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* ep93xx_spi_cleanup() - cleans up master controller specific state
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* @spi: SPI device to cleanup
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*
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* This function releases master controller specific state for given @spi
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* device.
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*/
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static void ep93xx_spi_cleanup(struct spi_device *spi)
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{
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struct ep93xx_spi_chip *chip;
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chip = spi_get_ctldata(spi);
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if (chip) {
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if (chip->ops && chip->ops->cleanup)
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chip->ops->cleanup(spi);
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spi_set_ctldata(spi, NULL);
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kfree(chip);
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}
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}
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/**
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* ep93xx_spi_chip_setup() - configures hardware according to given @chip
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* @espi: ep93xx SPI controller struct
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* @chip: chip specific settings
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* @speed_hz: transfer speed
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* @bits_per_word: transfer bits_per_word
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*/
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static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
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const struct ep93xx_spi_chip *chip,
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u32 speed_hz, u8 bits_per_word)
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{
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u8 dss = bits_per_word_to_dss(bits_per_word);
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u8 div_cpsr = 0;
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u8 div_scr = 0;
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u16 cr0;
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int err;
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err = ep93xx_spi_calc_divisors(espi, speed_hz, &div_cpsr, &div_scr);
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if (err)
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return err;
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cr0 = div_scr << SSPCR0_SCR_SHIFT;
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cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT;
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cr0 |= dss;
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dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
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chip->spi->mode, div_cpsr, div_scr, dss);
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dev_dbg(&espi->pdev->dev, "setup: cr0 %#x\n", cr0);
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ep93xx_spi_write_u8(espi, SSPCPSR, div_cpsr);
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ep93xx_spi_write_u16(espi, SSPCR0, cr0);
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return 0;
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}
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static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
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{
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if (t->bits_per_word > 8) {
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u16 tx_val = 0;
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if (t->tx_buf)
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tx_val = ((u16 *)t->tx_buf)[espi->tx];
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ep93xx_spi_write_u16(espi, SSPDR, tx_val);
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espi->tx += sizeof(tx_val);
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} else {
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u8 tx_val = 0;
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if (t->tx_buf)
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tx_val = ((u8 *)t->tx_buf)[espi->tx];
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ep93xx_spi_write_u8(espi, SSPDR, tx_val);
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espi->tx += sizeof(tx_val);
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}
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}
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static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
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{
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if (t->bits_per_word > 8) {
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u16 rx_val;
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rx_val = ep93xx_spi_read_u16(espi, SSPDR);
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if (t->rx_buf)
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((u16 *)t->rx_buf)[espi->rx] = rx_val;
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espi->rx += sizeof(rx_val);
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} else {
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u8 rx_val;
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rx_val = ep93xx_spi_read_u8(espi, SSPDR);
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if (t->rx_buf)
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((u8 *)t->rx_buf)[espi->rx] = rx_val;
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espi->rx += sizeof(rx_val);
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}
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}
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/**
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* ep93xx_spi_read_write() - perform next RX/TX transfer
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* @espi: ep93xx SPI controller struct
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*
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* This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
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* called several times, the whole transfer will be completed. Returns
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* %-EINPROGRESS when current transfer was not yet completed otherwise %0.
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*
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* When this function is finished, RX FIFO should be empty and TX FIFO should be
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* full.
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*/
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static int ep93xx_spi_read_write(struct ep93xx_spi *espi)
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{
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struct spi_message *msg = espi->current_msg;
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struct spi_transfer *t = msg->state;
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/* read as long as RX FIFO has frames in it */
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while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) {
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ep93xx_do_read(espi, t);
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espi->fifo_level--;
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}
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/* write as long as TX FIFO has room */
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while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) {
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ep93xx_do_write(espi, t);
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espi->fifo_level++;
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}
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if (espi->rx == t->len)
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return 0;
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return -EINPROGRESS;
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}
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static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
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{
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/*
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* Now everything is set up for the current transfer. We prime the TX
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* FIFO, enable interrupts, and wait for the transfer to complete.
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*/
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if (ep93xx_spi_read_write(espi)) {
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ep93xx_spi_enable_interrupts(espi);
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wait_for_completion(&espi->wait);
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}
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}
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/**
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* ep93xx_spi_dma_prepare() - prepares a DMA transfer
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* @espi: ep93xx SPI controller struct
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* @dir: DMA transfer direction
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*
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* Function configures the DMA, maps the buffer and prepares the DMA
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* descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
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* in case of failure.
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*/
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static struct dma_async_tx_descriptor *
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ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
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{
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struct spi_transfer *t = espi->current_msg->state;
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struct dma_async_tx_descriptor *txd;
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enum dma_slave_buswidth buswidth;
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struct dma_slave_config conf;
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struct scatterlist *sg;
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struct sg_table *sgt;
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struct dma_chan *chan;
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const void *buf, *pbuf;
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size_t len = t->len;
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int i, ret, nents;
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if (t->bits_per_word > 8)
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buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
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else
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buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
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memset(&conf, 0, sizeof(conf));
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conf.direction = dir;
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if (dir == DMA_DEV_TO_MEM) {
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chan = espi->dma_rx;
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buf = t->rx_buf;
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sgt = &espi->rx_sgt;
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conf.src_addr = espi->sspdr_phys;
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conf.src_addr_width = buswidth;
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} else {
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chan = espi->dma_tx;
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buf = t->tx_buf;
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sgt = &espi->tx_sgt;
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conf.dst_addr = espi->sspdr_phys;
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conf.dst_addr_width = buswidth;
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}
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ret = dmaengine_slave_config(chan, &conf);
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if (ret)
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return ERR_PTR(ret);
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/*
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* We need to split the transfer into PAGE_SIZE'd chunks. This is
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* because we are using @espi->zeropage to provide a zero RX buffer
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* for the TX transfers and we have only allocated one page for that.
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*
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* For performance reasons we allocate a new sg_table only when
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* needed. Otherwise we will re-use the current one. Eventually the
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* last sg_table is released in ep93xx_spi_release_dma().
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*/
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|
|
nents = DIV_ROUND_UP(len, PAGE_SIZE);
|
|
if (nents != sgt->nents) {
|
|
sg_free_table(sgt);
|
|
|
|
ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
|
|
if (ret)
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
pbuf = buf;
|
|
for_each_sg(sgt->sgl, sg, sgt->nents, i) {
|
|
size_t bytes = min_t(size_t, len, PAGE_SIZE);
|
|
|
|
if (buf) {
|
|
sg_set_page(sg, virt_to_page(pbuf), bytes,
|
|
offset_in_page(pbuf));
|
|
} else {
|
|
sg_set_page(sg, virt_to_page(espi->zeropage),
|
|
bytes, 0);
|
|
}
|
|
|
|
pbuf += bytes;
|
|
len -= bytes;
|
|
}
|
|
|
|
if (WARN_ON(len)) {
|
|
dev_warn(&espi->pdev->dev, "len = %zu expected 0!\n", len);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
|
|
if (!nents)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK);
|
|
if (!txd) {
|
|
dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
|
|
return ERR_PTR(-ENOMEM);
|
|
}
|
|
return txd;
|
|
}
|
|
|
|
/**
|
|
* ep93xx_spi_dma_finish() - finishes with a DMA transfer
|
|
* @espi: ep93xx SPI controller struct
|
|
* @dir: DMA transfer direction
|
|
*
|
|
* Function finishes with the DMA transfer. After this, the DMA buffer is
|
|
* unmapped.
|
|
*/
|
|
static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi,
|
|
enum dma_transfer_direction dir)
|
|
{
|
|
struct dma_chan *chan;
|
|
struct sg_table *sgt;
|
|
|
|
if (dir == DMA_DEV_TO_MEM) {
|
|
chan = espi->dma_rx;
|
|
sgt = &espi->rx_sgt;
|
|
} else {
|
|
chan = espi->dma_tx;
|
|
sgt = &espi->tx_sgt;
|
|
}
|
|
|
|
dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
|
|
}
|
|
|
|
static void ep93xx_spi_dma_callback(void *callback_param)
|
|
{
|
|
complete(callback_param);
|
|
}
|
|
|
|
static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi)
|
|
{
|
|
struct spi_message *msg = espi->current_msg;
|
|
struct dma_async_tx_descriptor *rxd, *txd;
|
|
|
|
rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM);
|
|
if (IS_ERR(rxd)) {
|
|
dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
|
|
msg->status = PTR_ERR(rxd);
|
|
return;
|
|
}
|
|
|
|
txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV);
|
|
if (IS_ERR(txd)) {
|
|
ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
|
|
dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(txd));
|
|
msg->status = PTR_ERR(txd);
|
|
return;
|
|
}
|
|
|
|
/* We are ready when RX is done */
|
|
rxd->callback = ep93xx_spi_dma_callback;
|
|
rxd->callback_param = &espi->wait;
|
|
|
|
/* Now submit both descriptors and wait while they finish */
|
|
dmaengine_submit(rxd);
|
|
dmaengine_submit(txd);
|
|
|
|
dma_async_issue_pending(espi->dma_rx);
|
|
dma_async_issue_pending(espi->dma_tx);
|
|
|
|
wait_for_completion(&espi->wait);
|
|
|
|
ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV);
|
|
ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
|
|
}
|
|
|
|
/**
|
|
* ep93xx_spi_process_transfer() - processes one SPI transfer
|
|
* @espi: ep93xx SPI controller struct
|
|
* @msg: current message
|
|
* @t: transfer to process
|
|
*
|
|
* This function processes one SPI transfer given in @t. Function waits until
|
|
* transfer is complete (may sleep) and updates @msg->status based on whether
|
|
* transfer was successfully processed or not.
|
|
*/
|
|
static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
|
|
struct spi_message *msg,
|
|
struct spi_transfer *t)
|
|
{
|
|
struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi);
|
|
int err;
|
|
|
|
msg->state = t;
|
|
|
|
err = ep93xx_spi_chip_setup(espi, chip, t->speed_hz, t->bits_per_word);
|
|
if (err) {
|
|
dev_err(&espi->pdev->dev,
|
|
"failed to setup chip for transfer\n");
|
|
msg->status = err;
|
|
return;
|
|
}
|
|
|
|
espi->rx = 0;
|
|
espi->tx = 0;
|
|
|
|
/*
|
|
* There is no point of setting up DMA for the transfers which will
|
|
* fit into the FIFO and can be transferred with a single interrupt.
|
|
* So in these cases we will be using PIO and don't bother for DMA.
|
|
*/
|
|
if (espi->dma_rx && t->len > SPI_FIFO_SIZE)
|
|
ep93xx_spi_dma_transfer(espi);
|
|
else
|
|
ep93xx_spi_pio_transfer(espi);
|
|
|
|
/*
|
|
* In case of error during transmit, we bail out from processing
|
|
* the message.
|
|
*/
|
|
if (msg->status)
|
|
return;
|
|
|
|
msg->actual_length += t->len;
|
|
|
|
/*
|
|
* After this transfer is finished, perform any possible
|
|
* post-transfer actions requested by the protocol driver.
|
|
*/
|
|
if (t->delay_usecs) {
|
|
set_current_state(TASK_UNINTERRUPTIBLE);
|
|
schedule_timeout(usecs_to_jiffies(t->delay_usecs));
|
|
}
|
|
if (t->cs_change) {
|
|
if (!list_is_last(&t->transfer_list, &msg->transfers)) {
|
|
/*
|
|
* In case protocol driver is asking us to drop the
|
|
* chipselect briefly, we let the scheduler to handle
|
|
* any "delay" here.
|
|
*/
|
|
ep93xx_spi_cs_control(msg->spi, false);
|
|
cond_resched();
|
|
ep93xx_spi_cs_control(msg->spi, true);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* ep93xx_spi_process_message() - process one SPI message
|
|
* @espi: ep93xx SPI controller struct
|
|
* @msg: message to process
|
|
*
|
|
* This function processes a single SPI message. We go through all transfers in
|
|
* the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
|
|
* asserted during the whole message (unless per transfer cs_change is set).
|
|
*
|
|
* @msg->status contains %0 in case of success or negative error code in case of
|
|
* failure.
|
|
*/
|
|
static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
|
|
struct spi_message *msg)
|
|
{
|
|
unsigned long timeout;
|
|
struct spi_transfer *t;
|
|
int err;
|
|
|
|
/*
|
|
* Enable the SPI controller and its clock.
|
|
*/
|
|
err = ep93xx_spi_enable(espi);
|
|
if (err) {
|
|
dev_err(&espi->pdev->dev, "failed to enable SPI controller\n");
|
|
msg->status = err;
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Just to be sure: flush any data from RX FIFO.
|
|
*/
|
|
timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
|
|
while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) {
|
|
if (time_after(jiffies, timeout)) {
|
|
dev_warn(&espi->pdev->dev,
|
|
"timeout while flushing RX FIFO\n");
|
|
msg->status = -ETIMEDOUT;
|
|
return;
|
|
}
|
|
ep93xx_spi_read_u16(espi, SSPDR);
|
|
}
|
|
|
|
/*
|
|
* We explicitly handle FIFO level. This way we don't have to check TX
|
|
* FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
|
|
*/
|
|
espi->fifo_level = 0;
|
|
|
|
/*
|
|
* Assert the chipselect.
|
|
*/
|
|
ep93xx_spi_cs_control(msg->spi, true);
|
|
|
|
list_for_each_entry(t, &msg->transfers, transfer_list) {
|
|
ep93xx_spi_process_transfer(espi, msg, t);
|
|
if (msg->status)
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Now the whole message is transferred (or failed for some reason). We
|
|
* deselect the device and disable the SPI controller.
|
|
*/
|
|
ep93xx_spi_cs_control(msg->spi, false);
|
|
ep93xx_spi_disable(espi);
|
|
}
|
|
|
|
static int ep93xx_spi_transfer_one_message(struct spi_master *master,
|
|
struct spi_message *msg)
|
|
{
|
|
struct ep93xx_spi *espi = spi_master_get_devdata(master);
|
|
|
|
msg->state = NULL;
|
|
msg->status = 0;
|
|
msg->actual_length = 0;
|
|
|
|
espi->current_msg = msg;
|
|
ep93xx_spi_process_message(espi, msg);
|
|
espi->current_msg = NULL;
|
|
|
|
spi_finalize_current_message(master);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct ep93xx_spi *espi = dev_id;
|
|
u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR);
|
|
|
|
/*
|
|
* If we got ROR (receive overrun) interrupt we know that something is
|
|
* wrong. Just abort the message.
|
|
*/
|
|
if (unlikely(irq_status & SSPIIR_RORIS)) {
|
|
/* clear the overrun interrupt */
|
|
ep93xx_spi_write_u8(espi, SSPICR, 0);
|
|
dev_warn(&espi->pdev->dev,
|
|
"receive overrun, aborting the message\n");
|
|
espi->current_msg->status = -EIO;
|
|
} else {
|
|
/*
|
|
* Interrupt is either RX (RIS) or TX (TIS). For both cases we
|
|
* simply execute next data transfer.
|
|
*/
|
|
if (ep93xx_spi_read_write(espi)) {
|
|
/*
|
|
* In normal case, there still is some processing left
|
|
* for current transfer. Let's wait for the next
|
|
* interrupt then.
|
|
*/
|
|
return IRQ_HANDLED;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Current transfer is finished, either with error or with success. In
|
|
* any case we disable interrupts and notify the worker to handle
|
|
* any post-processing of the message.
|
|
*/
|
|
ep93xx_spi_disable_interrupts(espi);
|
|
complete(&espi->wait);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
|
|
{
|
|
if (ep93xx_dma_chan_is_m2p(chan))
|
|
return false;
|
|
|
|
chan->private = filter_param;
|
|
return true;
|
|
}
|
|
|
|
static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
|
|
{
|
|
dma_cap_mask_t mask;
|
|
int ret;
|
|
|
|
espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
|
|
if (!espi->zeropage)
|
|
return -ENOMEM;
|
|
|
|
dma_cap_zero(mask);
|
|
dma_cap_set(DMA_SLAVE, mask);
|
|
|
|
espi->dma_rx_data.port = EP93XX_DMA_SSP;
|
|
espi->dma_rx_data.direction = DMA_DEV_TO_MEM;
|
|
espi->dma_rx_data.name = "ep93xx-spi-rx";
|
|
|
|
espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
|
|
&espi->dma_rx_data);
|
|
if (!espi->dma_rx) {
|
|
ret = -ENODEV;
|
|
goto fail_free_page;
|
|
}
|
|
|
|
espi->dma_tx_data.port = EP93XX_DMA_SSP;
|
|
espi->dma_tx_data.direction = DMA_MEM_TO_DEV;
|
|
espi->dma_tx_data.name = "ep93xx-spi-tx";
|
|
|
|
espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
|
|
&espi->dma_tx_data);
|
|
if (!espi->dma_tx) {
|
|
ret = -ENODEV;
|
|
goto fail_release_rx;
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail_release_rx:
|
|
dma_release_channel(espi->dma_rx);
|
|
espi->dma_rx = NULL;
|
|
fail_free_page:
|
|
free_page((unsigned long)espi->zeropage);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
|
|
{
|
|
if (espi->dma_rx) {
|
|
dma_release_channel(espi->dma_rx);
|
|
sg_free_table(&espi->rx_sgt);
|
|
}
|
|
if (espi->dma_tx) {
|
|
dma_release_channel(espi->dma_tx);
|
|
sg_free_table(&espi->tx_sgt);
|
|
}
|
|
|
|
if (espi->zeropage)
|
|
free_page((unsigned long)espi->zeropage);
|
|
}
|
|
|
|
static int ep93xx_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master;
|
|
struct ep93xx_spi_info *info;
|
|
struct ep93xx_spi *espi;
|
|
struct resource *res;
|
|
int irq;
|
|
int error;
|
|
|
|
info = dev_get_platdata(&pdev->dev);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "failed to get irq resources\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "unable to get iomem resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*espi));
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
master->setup = ep93xx_spi_setup;
|
|
master->transfer_one_message = ep93xx_spi_transfer_one_message;
|
|
master->cleanup = ep93xx_spi_cleanup;
|
|
master->bus_num = pdev->id;
|
|
master->num_chipselect = info->num_chipselect;
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
espi = spi_master_get_devdata(master);
|
|
|
|
espi->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(espi->clk)) {
|
|
dev_err(&pdev->dev, "unable to get spi clock\n");
|
|
error = PTR_ERR(espi->clk);
|
|
goto fail_release_master;
|
|
}
|
|
|
|
init_completion(&espi->wait);
|
|
|
|
/*
|
|
* Calculate maximum and minimum supported clock rates
|
|
* for the controller.
|
|
*/
|
|
master->max_speed_hz = clk_get_rate(espi->clk) / 2;
|
|
master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
|
|
espi->pdev = pdev;
|
|
|
|
espi->sspdr_phys = res->start + SSPDR;
|
|
|
|
espi->regs_base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(espi->regs_base)) {
|
|
error = PTR_ERR(espi->regs_base);
|
|
goto fail_release_master;
|
|
}
|
|
|
|
error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
|
|
0, "ep93xx-spi", espi);
|
|
if (error) {
|
|
dev_err(&pdev->dev, "failed to request irq\n");
|
|
goto fail_release_master;
|
|
}
|
|
|
|
if (info->use_dma && ep93xx_spi_setup_dma(espi))
|
|
dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
|
|
|
|
/* make sure that the hardware is disabled */
|
|
ep93xx_spi_write_u8(espi, SSPCR1, 0);
|
|
|
|
error = devm_spi_register_master(&pdev->dev, master);
|
|
if (error) {
|
|
dev_err(&pdev->dev, "failed to register SPI master\n");
|
|
goto fail_free_dma;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
|
|
(unsigned long)res->start, irq);
|
|
|
|
return 0;
|
|
|
|
fail_free_dma:
|
|
ep93xx_spi_release_dma(espi);
|
|
fail_release_master:
|
|
spi_master_put(master);
|
|
|
|
return error;
|
|
}
|
|
|
|
static int ep93xx_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct ep93xx_spi *espi = spi_master_get_devdata(master);
|
|
|
|
ep93xx_spi_release_dma(espi);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ep93xx_spi_driver = {
|
|
.driver = {
|
|
.name = "ep93xx-spi",
|
|
},
|
|
.probe = ep93xx_spi_probe,
|
|
.remove = ep93xx_spi_remove,
|
|
};
|
|
module_platform_driver(ep93xx_spi_driver);
|
|
|
|
MODULE_DESCRIPTION("EP93xx SPI Controller driver");
|
|
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:ep93xx-spi");
|