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c4c0efb06f
Before update thermal pressure, the max cpufreq should be limited. Add QOS control for Lmh throttle cpufreq. Signed-off-by: Xuewen Yan <xuewen.yan@unisoc.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
728 lines
18 KiB
C
728 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/cpufreq.h>
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#include <linux/init.h>
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#include <linux/interconnect.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_qos.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/units.h>
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#define LUT_MAX_ENTRIES 40U
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#define LUT_SRC GENMASK(31, 30)
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#define LUT_L_VAL GENMASK(7, 0)
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#define LUT_CORE_COUNT GENMASK(18, 16)
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#define LUT_VOLT GENMASK(11, 0)
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#define CLK_HW_DIV 2
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#define LUT_TURBO_IND 1
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#define GT_IRQ_STATUS BIT(2)
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struct qcom_cpufreq_soc_data {
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u32 reg_enable;
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u32 reg_domain_state;
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u32 reg_dcvs_ctrl;
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u32 reg_freq_lut;
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u32 reg_volt_lut;
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u32 reg_intr_clr;
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u32 reg_current_vote;
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u32 reg_perf_state;
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u8 lut_row_size;
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};
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struct qcom_cpufreq_data {
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void __iomem *base;
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struct resource *res;
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const struct qcom_cpufreq_soc_data *soc_data;
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/*
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* Mutex to synchronize between de-init sequence and re-starting LMh
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* polling/interrupts
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*/
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struct mutex throttle_lock;
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int throttle_irq;
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char irq_name[15];
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bool cancel_throttle;
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struct delayed_work throttle_work;
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struct cpufreq_policy *policy;
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bool per_core_dcvs;
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struct freq_qos_request throttle_freq_req;
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};
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static unsigned long cpu_hw_rate, xo_rate;
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static bool icc_scaling_enabled;
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static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
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unsigned long freq_khz)
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{
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unsigned long freq_hz = freq_khz * 1000;
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struct dev_pm_opp *opp;
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struct device *dev;
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int ret;
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dev = get_cpu_device(policy->cpu);
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if (!dev)
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return -ENODEV;
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opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
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if (IS_ERR(opp))
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return PTR_ERR(opp);
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ret = dev_pm_opp_set_opp(dev, opp);
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dev_pm_opp_put(opp);
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return ret;
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}
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static int qcom_cpufreq_update_opp(struct device *cpu_dev,
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unsigned long freq_khz,
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unsigned long volt)
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{
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unsigned long freq_hz = freq_khz * 1000;
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int ret;
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/* Skip voltage update if the opp table is not available */
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if (!icc_scaling_enabled)
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return dev_pm_opp_add(cpu_dev, freq_hz, volt);
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ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
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if (ret) {
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dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
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return ret;
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}
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return dev_pm_opp_enable(cpu_dev, freq_hz);
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}
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static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct qcom_cpufreq_data *data = policy->driver_data;
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const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
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unsigned long freq = policy->freq_table[index].frequency;
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unsigned int i;
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writel_relaxed(index, data->base + soc_data->reg_perf_state);
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if (data->per_core_dcvs)
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for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
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writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
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if (icc_scaling_enabled)
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qcom_cpufreq_set_bw(policy, freq);
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return 0;
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}
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static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
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{
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struct qcom_cpufreq_data *data;
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const struct qcom_cpufreq_soc_data *soc_data;
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struct cpufreq_policy *policy;
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unsigned int index;
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policy = cpufreq_cpu_get_raw(cpu);
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if (!policy)
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return 0;
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data = policy->driver_data;
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soc_data = data->soc_data;
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index = readl_relaxed(data->base + soc_data->reg_perf_state);
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index = min(index, LUT_MAX_ENTRIES - 1);
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return policy->freq_table[index].frequency;
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}
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static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
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unsigned int target_freq)
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{
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struct qcom_cpufreq_data *data = policy->driver_data;
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const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
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unsigned int index;
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unsigned int i;
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index = policy->cached_resolved_idx;
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writel_relaxed(index, data->base + soc_data->reg_perf_state);
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if (data->per_core_dcvs)
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for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
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writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
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return policy->freq_table[index].frequency;
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}
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static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
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struct cpufreq_policy *policy)
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{
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u32 data, src, lval, i, core_count, prev_freq = 0, freq;
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u32 volt;
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struct cpufreq_frequency_table *table;
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struct dev_pm_opp *opp;
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unsigned long rate;
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int ret;
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struct qcom_cpufreq_data *drv_data = policy->driver_data;
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const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
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table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
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if (!table)
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return -ENOMEM;
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ret = dev_pm_opp_of_add_table(cpu_dev);
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if (!ret) {
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/* Disable all opps and cross-validate against LUT later */
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icc_scaling_enabled = true;
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for (rate = 0; ; rate++) {
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opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
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if (IS_ERR(opp))
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break;
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dev_pm_opp_put(opp);
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dev_pm_opp_disable(cpu_dev, rate);
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}
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} else if (ret != -ENODEV) {
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dev_err(cpu_dev, "Invalid opp table in device tree\n");
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return ret;
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} else {
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policy->fast_switch_possible = true;
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icc_scaling_enabled = false;
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}
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for (i = 0; i < LUT_MAX_ENTRIES; i++) {
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data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
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i * soc_data->lut_row_size);
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src = FIELD_GET(LUT_SRC, data);
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lval = FIELD_GET(LUT_L_VAL, data);
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core_count = FIELD_GET(LUT_CORE_COUNT, data);
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data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
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i * soc_data->lut_row_size);
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volt = FIELD_GET(LUT_VOLT, data) * 1000;
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if (src)
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freq = xo_rate * lval / 1000;
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else
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freq = cpu_hw_rate / 1000;
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if (freq != prev_freq && core_count != LUT_TURBO_IND) {
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if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
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table[i].frequency = freq;
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dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
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freq, core_count);
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} else {
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dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
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table[i].frequency = CPUFREQ_ENTRY_INVALID;
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}
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} else if (core_count == LUT_TURBO_IND) {
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table[i].frequency = CPUFREQ_ENTRY_INVALID;
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}
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/*
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* Two of the same frequencies with the same core counts means
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* end of table
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*/
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if (i > 0 && prev_freq == freq) {
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struct cpufreq_frequency_table *prev = &table[i - 1];
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/*
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* Only treat the last frequency that might be a boost
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* as the boost frequency
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*/
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if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
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if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
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prev->frequency = prev_freq;
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prev->flags = CPUFREQ_BOOST_FREQ;
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} else {
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dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
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freq);
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}
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}
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break;
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}
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prev_freq = freq;
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}
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table[i].frequency = CPUFREQ_TABLE_END;
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policy->freq_table = table;
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dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
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return 0;
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}
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static void qcom_get_related_cpus(int index, struct cpumask *m)
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{
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struct device_node *cpu_np;
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struct of_phandle_args args;
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int cpu, ret;
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for_each_possible_cpu(cpu) {
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cpu_np = of_cpu_device_node_get(cpu);
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if (!cpu_np)
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continue;
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ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
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"#freq-domain-cells", 0,
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&args);
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of_node_put(cpu_np);
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if (ret < 0)
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continue;
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if (index == args.args[0])
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cpumask_set_cpu(cpu, m);
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}
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}
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static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
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{
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unsigned int lval;
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if (data->soc_data->reg_current_vote)
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lval = readl_relaxed(data->base + data->soc_data->reg_current_vote) & 0x3ff;
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else
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lval = readl_relaxed(data->base + data->soc_data->reg_domain_state) & 0xff;
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return lval * xo_rate;
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}
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static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
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{
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struct cpufreq_policy *policy = data->policy;
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int cpu = cpumask_first(policy->related_cpus);
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struct device *dev = get_cpu_device(cpu);
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unsigned long freq_hz, throttled_freq;
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struct dev_pm_opp *opp;
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/*
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* Get the h/w throttled frequency, normalize it using the
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* registered opp table and use it to calculate thermal pressure.
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*/
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freq_hz = qcom_lmh_get_throttle_freq(data);
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opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
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if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
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opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz);
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if (IS_ERR(opp)) {
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dev_warn(dev, "Can't find the OPP for throttling: %pe!\n", opp);
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} else {
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dev_pm_opp_put(opp);
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}
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throttled_freq = freq_hz / HZ_PER_KHZ;
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freq_qos_update_request(&data->throttle_freq_req, throttled_freq);
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/* Update thermal pressure (the boost frequencies are accepted) */
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arch_update_thermal_pressure(policy->related_cpus, throttled_freq);
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/*
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* In the unlikely case policy is unregistered do not enable
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* polling or h/w interrupt
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*/
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mutex_lock(&data->throttle_lock);
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if (data->cancel_throttle)
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goto out;
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/*
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* If h/w throttled frequency is higher than what cpufreq has requested
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* for, then stop polling and switch back to interrupt mechanism.
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*/
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if (throttled_freq >= qcom_cpufreq_hw_get(cpu))
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enable_irq(data->throttle_irq);
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else
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mod_delayed_work(system_highpri_wq, &data->throttle_work,
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msecs_to_jiffies(10));
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out:
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mutex_unlock(&data->throttle_lock);
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}
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static void qcom_lmh_dcvs_poll(struct work_struct *work)
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{
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struct qcom_cpufreq_data *data;
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data = container_of(work, struct qcom_cpufreq_data, throttle_work.work);
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qcom_lmh_dcvs_notify(data);
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}
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static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data)
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{
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struct qcom_cpufreq_data *c_data = data;
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/* Disable interrupt and enable polling */
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disable_irq_nosync(c_data->throttle_irq);
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schedule_delayed_work(&c_data->throttle_work, 0);
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if (c_data->soc_data->reg_intr_clr)
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writel_relaxed(GT_IRQ_STATUS,
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c_data->base + c_data->soc_data->reg_intr_clr);
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return IRQ_HANDLED;
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}
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static const struct qcom_cpufreq_soc_data qcom_soc_data = {
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.reg_enable = 0x0,
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.reg_dcvs_ctrl = 0xbc,
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.reg_freq_lut = 0x110,
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.reg_volt_lut = 0x114,
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.reg_current_vote = 0x704,
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.reg_perf_state = 0x920,
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.lut_row_size = 32,
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};
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static const struct qcom_cpufreq_soc_data epss_soc_data = {
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.reg_enable = 0x0,
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.reg_domain_state = 0x20,
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.reg_dcvs_ctrl = 0xb0,
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.reg_freq_lut = 0x100,
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.reg_volt_lut = 0x200,
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.reg_intr_clr = 0x308,
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.reg_perf_state = 0x320,
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.lut_row_size = 4,
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};
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static const struct of_device_id qcom_cpufreq_hw_match[] = {
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{ .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
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{ .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
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{}
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};
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MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
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static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
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{
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struct qcom_cpufreq_data *data = policy->driver_data;
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struct platform_device *pdev = cpufreq_get_driver_data();
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int ret;
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/*
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* Look for LMh interrupt. If no interrupt line is specified /
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* if there is an error, allow cpufreq to be enabled as usual.
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*/
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data->throttle_irq = platform_get_irq_optional(pdev, index);
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if (data->throttle_irq == -ENXIO)
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return 0;
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if (data->throttle_irq < 0)
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return data->throttle_irq;
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ret = freq_qos_add_request(&policy->constraints,
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&data->throttle_freq_req, FREQ_QOS_MAX,
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FREQ_QOS_MAX_DEFAULT_VALUE);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to add freq constraint (%d)\n", ret);
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return ret;
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}
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data->cancel_throttle = false;
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data->policy = policy;
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mutex_init(&data->throttle_lock);
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INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
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snprintf(data->irq_name, sizeof(data->irq_name), "dcvsh-irq-%u", policy->cpu);
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ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
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IRQF_ONESHOT | IRQF_NO_AUTOEN, data->irq_name, data);
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if (ret) {
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dev_err(&pdev->dev, "Error registering %s: %d\n", data->irq_name, ret);
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return 0;
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}
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ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
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if (ret)
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dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
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data->irq_name, data->throttle_irq);
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return 0;
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}
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static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy)
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{
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struct qcom_cpufreq_data *data = policy->driver_data;
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struct platform_device *pdev = cpufreq_get_driver_data();
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int ret;
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if (data->throttle_irq <= 0)
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return 0;
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mutex_lock(&data->throttle_lock);
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data->cancel_throttle = false;
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mutex_unlock(&data->throttle_lock);
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ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
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if (ret)
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dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
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data->irq_name, data->throttle_irq);
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return ret;
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}
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static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy)
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{
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struct qcom_cpufreq_data *data = policy->driver_data;
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if (data->throttle_irq <= 0)
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return 0;
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mutex_lock(&data->throttle_lock);
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data->cancel_throttle = true;
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mutex_unlock(&data->throttle_lock);
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cancel_delayed_work_sync(&data->throttle_work);
|
|
irq_set_affinity_and_hint(data->throttle_irq, NULL);
|
|
disable_irq_nosync(data->throttle_irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
|
|
{
|
|
if (data->throttle_irq <= 0)
|
|
return;
|
|
|
|
freq_qos_remove_request(&data->throttle_freq_req);
|
|
free_irq(data->throttle_irq, data);
|
|
}
|
|
|
|
static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
|
|
{
|
|
struct platform_device *pdev = cpufreq_get_driver_data();
|
|
struct device *dev = &pdev->dev;
|
|
struct of_phandle_args args;
|
|
struct device_node *cpu_np;
|
|
struct device *cpu_dev;
|
|
struct resource *res;
|
|
void __iomem *base;
|
|
struct qcom_cpufreq_data *data;
|
|
int ret, index;
|
|
|
|
cpu_dev = get_cpu_device(policy->cpu);
|
|
if (!cpu_dev) {
|
|
pr_err("%s: failed to get cpu%d device\n", __func__,
|
|
policy->cpu);
|
|
return -ENODEV;
|
|
}
|
|
|
|
cpu_np = of_cpu_device_node_get(policy->cpu);
|
|
if (!cpu_np)
|
|
return -EINVAL;
|
|
|
|
ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
|
|
"#freq-domain-cells", 0, &args);
|
|
of_node_put(cpu_np);
|
|
if (ret)
|
|
return ret;
|
|
|
|
index = args.args[0];
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, index);
|
|
if (!res) {
|
|
dev_err(dev, "failed to get mem resource %d\n", index);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!request_mem_region(res->start, resource_size(res), res->name)) {
|
|
dev_err(dev, "failed to request resource %pR\n", res);
|
|
return -EBUSY;
|
|
}
|
|
|
|
base = ioremap(res->start, resource_size(res));
|
|
if (!base) {
|
|
dev_err(dev, "failed to map resource %pR\n", res);
|
|
ret = -ENOMEM;
|
|
goto release_region;
|
|
}
|
|
|
|
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
|
if (!data) {
|
|
ret = -ENOMEM;
|
|
goto unmap_base;
|
|
}
|
|
|
|
data->soc_data = of_device_get_match_data(&pdev->dev);
|
|
data->base = base;
|
|
data->res = res;
|
|
|
|
/* HW should be in enabled state to proceed */
|
|
if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
|
|
dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
|
|
ret = -ENODEV;
|
|
goto error;
|
|
}
|
|
|
|
if (readl_relaxed(base + data->soc_data->reg_dcvs_ctrl) & 0x1)
|
|
data->per_core_dcvs = true;
|
|
|
|
qcom_get_related_cpus(index, policy->cpus);
|
|
if (cpumask_empty(policy->cpus)) {
|
|
dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
|
|
ret = -ENOENT;
|
|
goto error;
|
|
}
|
|
|
|
policy->driver_data = data;
|
|
policy->dvfs_possible_from_any_cpu = true;
|
|
|
|
ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
|
|
if (ret) {
|
|
dev_err(dev, "Domain-%d failed to read LUT\n", index);
|
|
goto error;
|
|
}
|
|
|
|
ret = dev_pm_opp_get_opp_count(cpu_dev);
|
|
if (ret <= 0) {
|
|
dev_err(cpu_dev, "Failed to add OPPs\n");
|
|
ret = -ENODEV;
|
|
goto error;
|
|
}
|
|
|
|
if (policy_has_boost_freq(policy)) {
|
|
ret = cpufreq_enable_boost_support();
|
|
if (ret)
|
|
dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
|
|
}
|
|
|
|
ret = qcom_cpufreq_hw_lmh_init(policy, index);
|
|
if (ret)
|
|
goto error;
|
|
|
|
return 0;
|
|
error:
|
|
kfree(data);
|
|
unmap_base:
|
|
iounmap(base);
|
|
release_region:
|
|
release_mem_region(res->start, resource_size(res));
|
|
return ret;
|
|
}
|
|
|
|
static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
|
|
{
|
|
struct device *cpu_dev = get_cpu_device(policy->cpu);
|
|
struct qcom_cpufreq_data *data = policy->driver_data;
|
|
struct resource *res = data->res;
|
|
void __iomem *base = data->base;
|
|
|
|
dev_pm_opp_remove_all_dynamic(cpu_dev);
|
|
dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
|
|
qcom_cpufreq_hw_lmh_exit(data);
|
|
kfree(policy->freq_table);
|
|
kfree(data);
|
|
iounmap(base);
|
|
release_mem_region(res->start, resource_size(res));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void qcom_cpufreq_ready(struct cpufreq_policy *policy)
|
|
{
|
|
struct qcom_cpufreq_data *data = policy->driver_data;
|
|
|
|
if (data->throttle_irq >= 0)
|
|
enable_irq(data->throttle_irq);
|
|
}
|
|
|
|
static struct freq_attr *qcom_cpufreq_hw_attr[] = {
|
|
&cpufreq_freq_attr_scaling_available_freqs,
|
|
&cpufreq_freq_attr_scaling_boost_freqs,
|
|
NULL
|
|
};
|
|
|
|
static struct cpufreq_driver cpufreq_qcom_hw_driver = {
|
|
.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
|
|
CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
|
|
CPUFREQ_IS_COOLING_DEV,
|
|
.verify = cpufreq_generic_frequency_table_verify,
|
|
.target_index = qcom_cpufreq_hw_target_index,
|
|
.get = qcom_cpufreq_hw_get,
|
|
.init = qcom_cpufreq_hw_cpu_init,
|
|
.exit = qcom_cpufreq_hw_cpu_exit,
|
|
.online = qcom_cpufreq_hw_cpu_online,
|
|
.offline = qcom_cpufreq_hw_cpu_offline,
|
|
.register_em = cpufreq_register_em_with_opp,
|
|
.fast_switch = qcom_cpufreq_hw_fast_switch,
|
|
.name = "qcom-cpufreq-hw",
|
|
.attr = qcom_cpufreq_hw_attr,
|
|
.ready = qcom_cpufreq_ready,
|
|
};
|
|
|
|
static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *cpu_dev;
|
|
struct clk *clk;
|
|
int ret;
|
|
|
|
clk = clk_get(&pdev->dev, "xo");
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
xo_rate = clk_get_rate(clk);
|
|
clk_put(clk);
|
|
|
|
clk = clk_get(&pdev->dev, "alternate");
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
|
|
clk_put(clk);
|
|
|
|
cpufreq_qcom_hw_driver.driver_data = pdev;
|
|
|
|
/* Check for optional interconnect paths on CPU0 */
|
|
cpu_dev = get_cpu_device(0);
|
|
if (!cpu_dev)
|
|
return -EPROBE_DEFER;
|
|
|
|
ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
|
|
if (ret)
|
|
dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
|
|
else
|
|
dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
|
|
{
|
|
return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
|
|
}
|
|
|
|
static struct platform_driver qcom_cpufreq_hw_driver = {
|
|
.probe = qcom_cpufreq_hw_driver_probe,
|
|
.remove = qcom_cpufreq_hw_driver_remove,
|
|
.driver = {
|
|
.name = "qcom-cpufreq-hw",
|
|
.of_match_table = qcom_cpufreq_hw_match,
|
|
},
|
|
};
|
|
|
|
static int __init qcom_cpufreq_hw_init(void)
|
|
{
|
|
return platform_driver_register(&qcom_cpufreq_hw_driver);
|
|
}
|
|
postcore_initcall(qcom_cpufreq_hw_init);
|
|
|
|
static void __exit qcom_cpufreq_hw_exit(void)
|
|
{
|
|
platform_driver_unregister(&qcom_cpufreq_hw_driver);
|
|
}
|
|
module_exit(qcom_cpufreq_hw_exit);
|
|
|
|
MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
|
|
MODULE_LICENSE("GPL v2");
|