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![Geert Uytterhoeven](/assets/img/avatar_default.png)
It does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. Add comments to clarify the purpose of the empty elements. Rewrap entries to a single line to have a consistent style. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru> Acked-by: Florian Fainelli <f.fainelli@gmail.com> [ahci_brcm] Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
188 lines
4.3 KiB
C
188 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* MediaTek AHCI SATA driver
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*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <linux/ahci_platform.h>
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#include <linux/kernel.h>
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#include <linux/libata.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "ahci.h"
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#define DRV_NAME "ahci-mtk"
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#define SYS_CFG 0x14
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#define SYS_CFG_SATA_MSK GENMASK(31, 30)
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#define SYS_CFG_SATA_EN BIT(31)
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struct mtk_ahci_plat {
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struct regmap *mode;
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struct reset_control *axi_rst;
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struct reset_control *sw_rst;
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struct reset_control *reg_rst;
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};
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static const struct ata_port_info ahci_port_info = {
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.flags = AHCI_FLAG_COMMON,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_platform_ops,
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};
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static struct scsi_host_template ahci_platform_sht = {
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AHCI_SHT(DRV_NAME),
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};
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static int mtk_ahci_platform_resets(struct ahci_host_priv *hpriv,
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struct device *dev)
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{
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struct mtk_ahci_plat *plat = hpriv->plat_data;
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int err;
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/* reset AXI bus and PHY part */
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plat->axi_rst = devm_reset_control_get_optional_exclusive(dev, "axi");
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if (PTR_ERR(plat->axi_rst) == -EPROBE_DEFER)
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return PTR_ERR(plat->axi_rst);
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plat->sw_rst = devm_reset_control_get_optional_exclusive(dev, "sw");
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if (PTR_ERR(plat->sw_rst) == -EPROBE_DEFER)
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return PTR_ERR(plat->sw_rst);
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plat->reg_rst = devm_reset_control_get_optional_exclusive(dev, "reg");
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if (PTR_ERR(plat->reg_rst) == -EPROBE_DEFER)
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return PTR_ERR(plat->reg_rst);
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err = reset_control_assert(plat->axi_rst);
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if (err) {
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dev_err(dev, "failed to assert AXI bus\n");
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return err;
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}
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err = reset_control_assert(plat->sw_rst);
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if (err) {
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dev_err(dev, "failed to assert PHY digital part\n");
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return err;
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}
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err = reset_control_assert(plat->reg_rst);
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if (err) {
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dev_err(dev, "failed to assert PHY register part\n");
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return err;
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}
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err = reset_control_deassert(plat->reg_rst);
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if (err) {
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dev_err(dev, "failed to deassert PHY register part\n");
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return err;
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}
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err = reset_control_deassert(plat->sw_rst);
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if (err) {
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dev_err(dev, "failed to deassert PHY digital part\n");
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return err;
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}
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err = reset_control_deassert(plat->axi_rst);
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if (err) {
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dev_err(dev, "failed to deassert AXI bus\n");
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return err;
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}
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return 0;
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}
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static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv,
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struct device *dev)
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{
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struct mtk_ahci_plat *plat = hpriv->plat_data;
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struct device_node *np = dev->of_node;
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/* enable SATA function if needed */
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if (of_find_property(np, "mediatek,phy-mode", NULL)) {
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plat->mode = syscon_regmap_lookup_by_phandle(
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np, "mediatek,phy-mode");
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if (IS_ERR(plat->mode)) {
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dev_err(dev, "missing phy-mode phandle\n");
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return PTR_ERR(plat->mode);
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}
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regmap_update_bits(plat->mode, SYS_CFG, SYS_CFG_SATA_MSK,
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SYS_CFG_SATA_EN);
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}
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of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map);
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return 0;
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}
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static int mtk_ahci_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_ahci_plat *plat;
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struct ahci_host_priv *hpriv;
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int err;
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plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);
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if (!plat)
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return -ENOMEM;
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hpriv = ahci_platform_get_resources(pdev, 0);
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if (IS_ERR(hpriv))
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return PTR_ERR(hpriv);
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hpriv->plat_data = plat;
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err = mtk_ahci_parse_property(hpriv, dev);
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if (err)
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return err;
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err = mtk_ahci_platform_resets(hpriv, dev);
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if (err)
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return err;
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err = ahci_platform_enable_resources(hpriv);
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if (err)
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return err;
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err = ahci_platform_init_host(pdev, hpriv, &ahci_port_info,
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&ahci_platform_sht);
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if (err)
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goto disable_resources;
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return 0;
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disable_resources:
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ahci_platform_disable_resources(hpriv);
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return err;
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}
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static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
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ahci_platform_resume);
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static const struct of_device_id ahci_of_match[] = {
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{ .compatible = "mediatek,mtk-ahci", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, ahci_of_match);
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static struct platform_driver mtk_ahci_driver = {
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.probe = mtk_ahci_probe,
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.remove = ata_platform_remove_one,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = ahci_of_match,
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.pm = &ahci_pm_ops,
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},
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};
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module_platform_driver(mtk_ahci_driver);
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MODULE_DESCRIPTION("MediaTek SATA AHCI Driver");
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MODULE_LICENSE("GPL v2");
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