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![Lin Yujun](/assets/img/avatar_default.png)
[ Upstream commit0e2c8e6d76
] Add platform_device_put() to make sure to free the platform device in the event platform_device_add() fails. Fixes:5184f4bf15
("clocksource/drivers/timer-gxp: Add HPE GXP Timer") Signed-off-by: Lin Yujun <linyujun809@huawei.com> Link: https://lore.kernel.org/r/20220914033018.97484-1-linyujun809@huawei.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
214 lines
5 KiB
C
214 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/sched_clock.h>
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#define TIMER0_FREQ 1000000
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#define GXP_TIMER_CNT_OFS 0x00
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#define GXP_TIMESTAMP_OFS 0x08
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#define GXP_TIMER_CTRL_OFS 0x14
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/* TCS Stands for Timer Control/Status: these are masks to be used in */
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/* the Timer Count Registers */
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#define MASK_TCS_ENABLE 0x01
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#define MASK_TCS_PERIOD 0x02
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#define MASK_TCS_RELOAD 0x04
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#define MASK_TCS_TC 0x80
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struct gxp_timer {
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void __iomem *counter;
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void __iomem *control;
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struct clock_event_device evt;
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};
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static struct gxp_timer *gxp_timer;
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static void __iomem *system_clock __ro_after_init;
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static inline struct gxp_timer *to_gxp_timer(struct clock_event_device *evt_dev)
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{
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return container_of(evt_dev, struct gxp_timer, evt);
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}
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static u64 notrace gxp_sched_read(void)
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{
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return readl_relaxed(system_clock);
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}
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static int gxp_time_set_next_event(unsigned long event, struct clock_event_device *evt_dev)
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{
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struct gxp_timer *timer = to_gxp_timer(evt_dev);
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/* Stop counting and disable interrupt before updating */
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writeb_relaxed(MASK_TCS_TC, timer->control);
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writel_relaxed(event, timer->counter);
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writeb_relaxed(MASK_TCS_TC | MASK_TCS_ENABLE, timer->control);
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return 0;
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}
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static irqreturn_t gxp_timer_interrupt(int irq, void *dev_id)
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{
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struct gxp_timer *timer = (struct gxp_timer *)dev_id;
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if (!(readb_relaxed(timer->control) & MASK_TCS_TC))
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return IRQ_NONE;
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writeb_relaxed(MASK_TCS_TC, timer->control);
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timer->evt.event_handler(&timer->evt);
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return IRQ_HANDLED;
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}
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static int __init gxp_timer_init(struct device_node *node)
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{
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void __iomem *base;
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struct clk *clk;
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u32 freq;
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int ret, irq;
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gxp_timer = kzalloc(sizeof(*gxp_timer), GFP_KERNEL);
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if (!gxp_timer) {
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ret = -ENOMEM;
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pr_err("Can't allocate gxp_timer");
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return ret;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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ret = (int)PTR_ERR(clk);
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pr_err("%pOFn clock not found: %d\n", node, ret);
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goto err_free;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("%pOFn clock enable failed: %d\n", node, ret);
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goto err_clk_enable;
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}
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base = of_iomap(node, 0);
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if (!base) {
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ret = -ENXIO;
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pr_err("Can't map timer base registers");
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goto err_iomap;
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}
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/* Set the offsets to the clock register and timer registers */
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gxp_timer->counter = base + GXP_TIMER_CNT_OFS;
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gxp_timer->control = base + GXP_TIMER_CTRL_OFS;
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system_clock = base + GXP_TIMESTAMP_OFS;
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gxp_timer->evt.name = node->name;
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gxp_timer->evt.rating = 300;
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gxp_timer->evt.features = CLOCK_EVT_FEAT_ONESHOT;
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gxp_timer->evt.set_next_event = gxp_time_set_next_event;
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gxp_timer->evt.cpumask = cpumask_of(0);
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0) {
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ret = -EINVAL;
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pr_err("GXP Timer Can't parse IRQ %d", irq);
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goto err_exit;
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}
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freq = clk_get_rate(clk);
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ret = clocksource_mmio_init(system_clock, node->name, freq,
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300, 32, clocksource_mmio_readl_up);
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if (ret) {
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pr_err("%pOFn init clocksource failed: %d", node, ret);
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goto err_exit;
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}
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sched_clock_register(gxp_sched_read, 32, freq);
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0) {
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ret = -EINVAL;
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pr_err("%pOFn Can't parse IRQ %d", node, irq);
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goto err_exit;
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}
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clockevents_config_and_register(&gxp_timer->evt, TIMER0_FREQ,
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0xf, 0xffffffff);
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ret = request_irq(irq, gxp_timer_interrupt, IRQF_TIMER | IRQF_SHARED,
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node->name, gxp_timer);
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if (ret) {
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pr_err("%pOFn request_irq() failed: %d", node, ret);
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goto err_exit;
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}
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pr_debug("gxp: system timer (irq = %d)\n", irq);
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return 0;
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err_exit:
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iounmap(base);
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err_iomap:
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clk_disable_unprepare(clk);
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err_clk_enable:
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clk_put(clk);
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err_free:
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kfree(gxp_timer);
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return ret;
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}
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/*
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* This probe gets called after the timer is already up and running. This will create
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* the watchdog device as a child since the registers are shared.
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*/
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static int gxp_timer_probe(struct platform_device *pdev)
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{
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struct platform_device *gxp_watchdog_device;
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struct device *dev = &pdev->dev;
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int ret;
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if (!gxp_timer) {
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pr_err("Gxp Timer not initialized, cannot create watchdog");
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return -ENOMEM;
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}
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gxp_watchdog_device = platform_device_alloc("gxp-wdt", -1);
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if (!gxp_watchdog_device) {
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pr_err("Timer failed to allocate gxp-wdt");
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return -ENOMEM;
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}
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/* Pass the base address (counter) as platform data and nothing else */
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gxp_watchdog_device->dev.platform_data = gxp_timer->counter;
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gxp_watchdog_device->dev.parent = dev;
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ret = platform_device_add(gxp_watchdog_device);
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if (ret)
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platform_device_put(gxp_watchdog_device);
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return ret;
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}
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static const struct of_device_id gxp_timer_of_match[] = {
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{ .compatible = "hpe,gxp-timer", },
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{},
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};
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static struct platform_driver gxp_timer_driver = {
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.probe = gxp_timer_probe,
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.driver = {
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.name = "gxp-timer",
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.of_match_table = gxp_timer_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(gxp_timer_driver);
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TIMER_OF_DECLARE(gxp, "hpe,gxp-timer", gxp_timer_init);
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