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![Linus Walleij](/assets/img/avatar_default.png)
The boardfiles for IXP4xx have been deleted. Delete all the quirks and code dealing with that boot path and rely solely on device tree boot. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220406205505.2332821-1-linus.walleij@linaro.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
293 lines
7.5 KiB
C
293 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* IXP4 timer driver
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* Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
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*
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* Based on arch/arm/mach-ixp4xx/common.c
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* Copyright 2002 (C) Intel Corporation
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* Copyright 2003-2004 (C) MontaVista, Software, Inc.
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* Copyright (C) Deepak Saxena <dsaxena@plexity.net>
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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/*
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* Constants to make it easy to access Timer Control/Status registers
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*/
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#define IXP4XX_OSTS_OFFSET 0x00 /* Continuous Timestamp */
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#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
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#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
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#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
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#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
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#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
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/*
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* Timer register values and bit definitions
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*/
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#define IXP4XX_OST_ENABLE 0x00000001
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#define IXP4XX_OST_ONE_SHOT 0x00000002
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/* Low order bits of reload value ignored */
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#define IXP4XX_OST_RELOAD_MASK 0x00000003
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#define IXP4XX_OST_DISABLED 0x00000000
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#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
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#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
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#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
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/* Remaining registers are for the watchdog and defined in the watchdog driver */
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struct ixp4xx_timer {
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void __iomem *base;
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u32 latch;
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struct clock_event_device clkevt;
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#ifdef CONFIG_ARM
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struct delay_timer delay_timer;
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#endif
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};
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/*
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* A local singleton used by sched_clock and delay timer reads, which are
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* fast and stateless
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*/
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static struct ixp4xx_timer *local_ixp4xx_timer;
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static inline struct ixp4xx_timer *
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to_ixp4xx_timer(struct clock_event_device *evt)
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{
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return container_of(evt, struct ixp4xx_timer, clkevt);
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}
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static unsigned long ixp4xx_read_timer(void)
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{
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return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET);
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}
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static u64 notrace ixp4xx_read_sched_clock(void)
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{
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return ixp4xx_read_timer();
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}
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static u64 ixp4xx_clocksource_read(struct clocksource *c)
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{
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return ixp4xx_read_timer();
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}
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static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
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{
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struct ixp4xx_timer *tmr = dev_id;
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struct clock_event_device *evt = &tmr->clkevt;
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/* Clear Pending Interrupt */
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__raw_writel(IXP4XX_OSST_TIMER_1_PEND,
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tmr->base + IXP4XX_OSST_OFFSET);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int ixp4xx_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
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u32 val;
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val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
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/* Keep enable/oneshot bits */
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val &= IXP4XX_OST_RELOAD_MASK;
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__raw_writel((cycles & ~IXP4XX_OST_RELOAD_MASK) | val,
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tmr->base + IXP4XX_OSRT1_OFFSET);
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return 0;
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}
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static int ixp4xx_shutdown(struct clock_event_device *evt)
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{
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struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
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u32 val;
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val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
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val &= ~IXP4XX_OST_ENABLE;
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__raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
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return 0;
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}
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static int ixp4xx_set_oneshot(struct clock_event_device *evt)
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{
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struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
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__raw_writel(IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT,
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tmr->base + IXP4XX_OSRT1_OFFSET);
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return 0;
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}
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static int ixp4xx_set_periodic(struct clock_event_device *evt)
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{
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struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
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u32 val;
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val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK;
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val |= IXP4XX_OST_ENABLE;
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__raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
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return 0;
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}
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static int ixp4xx_resume(struct clock_event_device *evt)
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{
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struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
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u32 val;
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val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
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val |= IXP4XX_OST_ENABLE;
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__raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
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return 0;
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}
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/*
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* IXP4xx timer tick
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* We use OS timer1 on the CPU for the timer tick and the timestamp
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* counter as a source of real clock ticks to account for missed jiffies.
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*/
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static __init int ixp4xx_timer_register(void __iomem *base,
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int timer_irq,
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unsigned int timer_freq)
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{
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struct ixp4xx_timer *tmr;
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int ret;
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tmr = kzalloc(sizeof(*tmr), GFP_KERNEL);
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if (!tmr)
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return -ENOMEM;
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tmr->base = base;
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/*
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* The timer register doesn't allow to specify the two least
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* significant bits of the timeout value and assumes them being zero.
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* So make sure the latch is the best value with the two least
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* significant bits unset.
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*/
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tmr->latch = DIV_ROUND_CLOSEST(timer_freq,
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(IXP4XX_OST_RELOAD_MASK + 1) * HZ)
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* (IXP4XX_OST_RELOAD_MASK + 1);
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local_ixp4xx_timer = tmr;
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/* Reset/disable counter */
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__raw_writel(0, tmr->base + IXP4XX_OSRT1_OFFSET);
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/* Clear any pending interrupt on timer 1 */
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__raw_writel(IXP4XX_OSST_TIMER_1_PEND,
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tmr->base + IXP4XX_OSST_OFFSET);
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/* Reset time-stamp counter */
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__raw_writel(0, tmr->base + IXP4XX_OSTS_OFFSET);
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clocksource_mmio_init(NULL, "OSTS", timer_freq, 200, 32,
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ixp4xx_clocksource_read);
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tmr->clkevt.name = "ixp4xx timer1";
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tmr->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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tmr->clkevt.rating = 200;
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tmr->clkevt.set_state_shutdown = ixp4xx_shutdown;
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tmr->clkevt.set_state_periodic = ixp4xx_set_periodic;
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tmr->clkevt.set_state_oneshot = ixp4xx_set_oneshot;
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tmr->clkevt.tick_resume = ixp4xx_resume;
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tmr->clkevt.set_next_event = ixp4xx_set_next_event;
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tmr->clkevt.cpumask = cpumask_of(0);
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tmr->clkevt.irq = timer_irq;
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ret = request_irq(timer_irq, ixp4xx_timer_interrupt,
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IRQF_TIMER, "IXP4XX-TIMER1", tmr);
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if (ret) {
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pr_crit("no timer IRQ\n");
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return -ENODEV;
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}
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clockevents_config_and_register(&tmr->clkevt, timer_freq,
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0xf, 0xfffffffe);
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sched_clock_register(ixp4xx_read_sched_clock, 32, timer_freq);
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#ifdef CONFIG_ARM
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/* Also use this timer for delays */
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tmr->delay_timer.read_current_timer = ixp4xx_read_timer;
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tmr->delay_timer.freq = timer_freq;
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register_current_timer_delay(&tmr->delay_timer);
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#endif
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return 0;
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}
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static struct platform_device ixp4xx_watchdog_device = {
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.name = "ixp4xx-watchdog",
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.id = -1,
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};
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/*
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* This probe gets called after the timer is already up and running. The main
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* function on this platform is to spawn the watchdog device as a child.
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*/
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static int ixp4xx_timer_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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/* Pass the base address as platform data and nothing else */
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ixp4xx_watchdog_device.dev.platform_data = local_ixp4xx_timer->base;
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ixp4xx_watchdog_device.dev.parent = dev;
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return platform_device_register(&ixp4xx_watchdog_device);
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}
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static const struct of_device_id ixp4xx_timer_dt_id[] = {
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{ .compatible = "intel,ixp4xx-timer", },
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{ /* sentinel */ },
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};
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static struct platform_driver ixp4xx_timer_driver = {
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.probe = ixp4xx_timer_probe,
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.driver = {
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.name = "ixp4xx-timer",
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.of_match_table = ixp4xx_timer_dt_id,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(ixp4xx_timer_driver);
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static __init int ixp4xx_of_timer_init(struct device_node *np)
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{
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void __iomem *base;
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int irq;
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int ret;
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base = of_iomap(np, 0);
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if (!base) {
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pr_crit("IXP4xx: can't remap timer\n");
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return -ENODEV;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (irq <= 0) {
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pr_err("Can't parse IRQ\n");
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ret = -EINVAL;
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goto out_unmap;
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}
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/* TODO: get some fixed clocks into the device tree */
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ret = ixp4xx_timer_register(base, irq, 66666000);
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if (ret)
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goto out_unmap;
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return 0;
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out_unmap:
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iounmap(base);
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return ret;
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}
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TIMER_OF_DECLARE(ixp4xx, "intel,ixp4xx-timer", ixp4xx_of_timer_init);
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