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![Eric Biggers](/assets/img/avatar_default.png)
Currently <crypto/sha.h> contains declarations for both SHA-1 and SHA-2, and <crypto/sha3.h> contains declarations for SHA-3. This organization is inconsistent, but more importantly SHA-1 is no longer considered to be cryptographically secure. So to the extent possible, SHA-1 shouldn't be grouped together with any of the other SHA versions, and usage of it should be phased out. Therefore, split <crypto/sha.h> into two headers <crypto/sha1.h> and <crypto/sha2.h>, and make everyone explicitly specify whether they want the declarations for SHA-1, SHA-2, or both. This avoids making the SHA-1 declarations visible to files that don't want anything to do with SHA-1. It also prepares for potentially moving sha1.h into a new insecure/ or dangerous/ directory. Signed-off-by: Eric Biggers <ebiggers@google.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
562 lines
15 KiB
C
562 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Cryptographic API.
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*
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* Support for VIA PadLock hardware crypto engine.
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*
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* Copyright (c) 2006 Michal Ludvig <michal@logix.cz>
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*/
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#include <crypto/internal/hash.h>
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#include <crypto/padlock.h>
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#include <crypto/sha1.h>
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#include <crypto/sha2.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/scatterlist.h>
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#include <asm/cpu_device_id.h>
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#include <asm/fpu/api.h>
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struct padlock_sha_desc {
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struct shash_desc fallback;
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};
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struct padlock_sha_ctx {
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struct crypto_shash *fallback;
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};
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static int padlock_sha_init(struct shash_desc *desc)
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{
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struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
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struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);
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dctx->fallback.tfm = ctx->fallback;
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return crypto_shash_init(&dctx->fallback);
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}
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static int padlock_sha_update(struct shash_desc *desc,
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const u8 *data, unsigned int length)
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{
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struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
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return crypto_shash_update(&dctx->fallback, data, length);
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}
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static int padlock_sha_export(struct shash_desc *desc, void *out)
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{
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struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
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return crypto_shash_export(&dctx->fallback, out);
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}
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static int padlock_sha_import(struct shash_desc *desc, const void *in)
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{
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struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
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struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);
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dctx->fallback.tfm = ctx->fallback;
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return crypto_shash_import(&dctx->fallback, in);
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}
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static inline void padlock_output_block(uint32_t *src,
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uint32_t *dst, size_t count)
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{
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while (count--)
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*dst++ = swab32(*src++);
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}
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static int padlock_sha1_finup(struct shash_desc *desc, const u8 *in,
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unsigned int count, u8 *out)
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{
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/* We can't store directly to *out as it may be unaligned. */
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/* BTW Don't reduce the buffer size below 128 Bytes!
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* PadLock microcode needs it that big. */
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char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
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((aligned(STACK_ALIGN)));
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char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
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struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
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struct sha1_state state;
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unsigned int space;
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unsigned int leftover;
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int err;
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err = crypto_shash_export(&dctx->fallback, &state);
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if (err)
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goto out;
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if (state.count + count > ULONG_MAX)
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return crypto_shash_finup(&dctx->fallback, in, count, out);
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leftover = ((state.count - 1) & (SHA1_BLOCK_SIZE - 1)) + 1;
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space = SHA1_BLOCK_SIZE - leftover;
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if (space) {
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if (count > space) {
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err = crypto_shash_update(&dctx->fallback, in, space) ?:
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crypto_shash_export(&dctx->fallback, &state);
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if (err)
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goto out;
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count -= space;
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in += space;
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} else {
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memcpy(state.buffer + leftover, in, count);
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in = state.buffer;
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count += leftover;
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state.count &= ~(SHA1_BLOCK_SIZE - 1);
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}
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}
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memcpy(result, &state.state, SHA1_DIGEST_SIZE);
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asm volatile (".byte 0xf3,0x0f,0xa6,0xc8" /* rep xsha1 */
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: \
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: "c"((unsigned long)state.count + count), \
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"a"((unsigned long)state.count), \
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"S"(in), "D"(result));
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padlock_output_block((uint32_t *)result, (uint32_t *)out, 5);
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out:
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return err;
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}
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static int padlock_sha1_final(struct shash_desc *desc, u8 *out)
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{
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u8 buf[4];
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return padlock_sha1_finup(desc, buf, 0, out);
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}
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static int padlock_sha256_finup(struct shash_desc *desc, const u8 *in,
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unsigned int count, u8 *out)
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{
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/* We can't store directly to *out as it may be unaligned. */
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/* BTW Don't reduce the buffer size below 128 Bytes!
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* PadLock microcode needs it that big. */
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char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
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((aligned(STACK_ALIGN)));
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char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
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struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
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struct sha256_state state;
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unsigned int space;
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unsigned int leftover;
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int err;
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err = crypto_shash_export(&dctx->fallback, &state);
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if (err)
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goto out;
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if (state.count + count > ULONG_MAX)
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return crypto_shash_finup(&dctx->fallback, in, count, out);
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leftover = ((state.count - 1) & (SHA256_BLOCK_SIZE - 1)) + 1;
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space = SHA256_BLOCK_SIZE - leftover;
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if (space) {
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if (count > space) {
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err = crypto_shash_update(&dctx->fallback, in, space) ?:
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crypto_shash_export(&dctx->fallback, &state);
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if (err)
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goto out;
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count -= space;
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in += space;
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} else {
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memcpy(state.buf + leftover, in, count);
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in = state.buf;
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count += leftover;
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state.count &= ~(SHA1_BLOCK_SIZE - 1);
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}
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}
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memcpy(result, &state.state, SHA256_DIGEST_SIZE);
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asm volatile (".byte 0xf3,0x0f,0xa6,0xd0" /* rep xsha256 */
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: \
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: "c"((unsigned long)state.count + count), \
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"a"((unsigned long)state.count), \
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"S"(in), "D"(result));
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padlock_output_block((uint32_t *)result, (uint32_t *)out, 8);
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out:
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return err;
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}
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static int padlock_sha256_final(struct shash_desc *desc, u8 *out)
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{
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u8 buf[4];
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return padlock_sha256_finup(desc, buf, 0, out);
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}
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static int padlock_init_tfm(struct crypto_shash *hash)
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{
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const char *fallback_driver_name = crypto_shash_alg_name(hash);
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struct padlock_sha_ctx *ctx = crypto_shash_ctx(hash);
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struct crypto_shash *fallback_tfm;
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/* Allocate a fallback and abort if it failed. */
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fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
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CRYPTO_ALG_NEED_FALLBACK);
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if (IS_ERR(fallback_tfm)) {
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printk(KERN_WARNING PFX "Fallback driver '%s' could not be loaded!\n",
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fallback_driver_name);
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return PTR_ERR(fallback_tfm);
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}
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ctx->fallback = fallback_tfm;
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hash->descsize += crypto_shash_descsize(fallback_tfm);
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return 0;
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}
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static void padlock_exit_tfm(struct crypto_shash *hash)
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{
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struct padlock_sha_ctx *ctx = crypto_shash_ctx(hash);
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crypto_free_shash(ctx->fallback);
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}
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static struct shash_alg sha1_alg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = padlock_sha_init,
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.update = padlock_sha_update,
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.finup = padlock_sha1_finup,
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.final = padlock_sha1_final,
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.export = padlock_sha_export,
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.import = padlock_sha_import,
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.init_tfm = padlock_init_tfm,
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.exit_tfm = padlock_exit_tfm,
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.descsize = sizeof(struct padlock_sha_desc),
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.statesize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name = "sha1-padlock",
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.cra_priority = PADLOCK_CRA_PRIORITY,
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.cra_flags = CRYPTO_ALG_NEED_FALLBACK,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct padlock_sha_ctx),
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.cra_module = THIS_MODULE,
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}
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};
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static struct shash_alg sha256_alg = {
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.digestsize = SHA256_DIGEST_SIZE,
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.init = padlock_sha_init,
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.update = padlock_sha_update,
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.finup = padlock_sha256_finup,
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.final = padlock_sha256_final,
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.export = padlock_sha_export,
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.import = padlock_sha_import,
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.init_tfm = padlock_init_tfm,
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.exit_tfm = padlock_exit_tfm,
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.descsize = sizeof(struct padlock_sha_desc),
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.statesize = sizeof(struct sha256_state),
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.base = {
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.cra_name = "sha256",
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.cra_driver_name = "sha256-padlock",
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.cra_priority = PADLOCK_CRA_PRIORITY,
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.cra_flags = CRYPTO_ALG_NEED_FALLBACK,
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.cra_blocksize = SHA256_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct padlock_sha_ctx),
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.cra_module = THIS_MODULE,
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}
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};
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/* Add two shash_alg instance for hardware-implemented *
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* multiple-parts hash supported by VIA Nano Processor.*/
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static int padlock_sha1_init_nano(struct shash_desc *desc)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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*sctx = (struct sha1_state){
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.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
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};
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return 0;
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}
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static int padlock_sha1_update_nano(struct shash_desc *desc,
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const u8 *data, unsigned int len)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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unsigned int partial, done;
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const u8 *src;
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/*The PHE require the out buffer must 128 bytes and 16-bytes aligned*/
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u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
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((aligned(STACK_ALIGN)));
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u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
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partial = sctx->count & 0x3f;
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sctx->count += len;
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done = 0;
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src = data;
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memcpy(dst, (u8 *)(sctx->state), SHA1_DIGEST_SIZE);
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if ((partial + len) >= SHA1_BLOCK_SIZE) {
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/* Append the bytes in state's buffer to a block to handle */
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if (partial) {
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done = -partial;
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memcpy(sctx->buffer + partial, data,
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done + SHA1_BLOCK_SIZE);
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src = sctx->buffer;
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asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
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: "+S"(src), "+D"(dst) \
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: "a"((long)-1), "c"((unsigned long)1));
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done += SHA1_BLOCK_SIZE;
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src = data + done;
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}
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/* Process the left bytes from the input data */
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if (len - done >= SHA1_BLOCK_SIZE) {
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asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
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: "+S"(src), "+D"(dst)
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: "a"((long)-1),
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"c"((unsigned long)((len - done) / SHA1_BLOCK_SIZE)));
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done += ((len - done) - (len - done) % SHA1_BLOCK_SIZE);
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src = data + done;
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}
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partial = 0;
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}
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memcpy((u8 *)(sctx->state), dst, SHA1_DIGEST_SIZE);
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memcpy(sctx->buffer + partial, src, len - done);
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return 0;
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}
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static int padlock_sha1_final_nano(struct shash_desc *desc, u8 *out)
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{
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struct sha1_state *state = (struct sha1_state *)shash_desc_ctx(desc);
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unsigned int partial, padlen;
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__be64 bits;
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static const u8 padding[64] = { 0x80, };
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bits = cpu_to_be64(state->count << 3);
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/* Pad out to 56 mod 64 */
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partial = state->count & 0x3f;
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padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
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padlock_sha1_update_nano(desc, padding, padlen);
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/* Append length field bytes */
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padlock_sha1_update_nano(desc, (const u8 *)&bits, sizeof(bits));
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/* Swap to output */
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padlock_output_block((uint32_t *)(state->state), (uint32_t *)out, 5);
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return 0;
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}
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static int padlock_sha256_init_nano(struct shash_desc *desc)
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{
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struct sha256_state *sctx = shash_desc_ctx(desc);
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*sctx = (struct sha256_state){
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.state = { SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, \
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SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7},
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};
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return 0;
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}
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static int padlock_sha256_update_nano(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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struct sha256_state *sctx = shash_desc_ctx(desc);
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unsigned int partial, done;
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const u8 *src;
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/*The PHE require the out buffer must 128 bytes and 16-bytes aligned*/
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u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
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((aligned(STACK_ALIGN)));
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u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
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partial = sctx->count & 0x3f;
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sctx->count += len;
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done = 0;
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src = data;
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memcpy(dst, (u8 *)(sctx->state), SHA256_DIGEST_SIZE);
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if ((partial + len) >= SHA256_BLOCK_SIZE) {
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/* Append the bytes in state's buffer to a block to handle */
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if (partial) {
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done = -partial;
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memcpy(sctx->buf + partial, data,
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done + SHA256_BLOCK_SIZE);
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src = sctx->buf;
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asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
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: "+S"(src), "+D"(dst)
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: "a"((long)-1), "c"((unsigned long)1));
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done += SHA256_BLOCK_SIZE;
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src = data + done;
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}
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/* Process the left bytes from input data*/
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if (len - done >= SHA256_BLOCK_SIZE) {
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asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
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: "+S"(src), "+D"(dst)
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: "a"((long)-1),
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"c"((unsigned long)((len - done) / 64)));
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done += ((len - done) - (len - done) % 64);
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src = data + done;
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}
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partial = 0;
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}
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memcpy((u8 *)(sctx->state), dst, SHA256_DIGEST_SIZE);
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memcpy(sctx->buf + partial, src, len - done);
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return 0;
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}
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static int padlock_sha256_final_nano(struct shash_desc *desc, u8 *out)
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{
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struct sha256_state *state =
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(struct sha256_state *)shash_desc_ctx(desc);
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unsigned int partial, padlen;
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__be64 bits;
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static const u8 padding[64] = { 0x80, };
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bits = cpu_to_be64(state->count << 3);
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/* Pad out to 56 mod 64 */
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partial = state->count & 0x3f;
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padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
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padlock_sha256_update_nano(desc, padding, padlen);
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/* Append length field bytes */
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padlock_sha256_update_nano(desc, (const u8 *)&bits, sizeof(bits));
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/* Swap to output */
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padlock_output_block((uint32_t *)(state->state), (uint32_t *)out, 8);
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return 0;
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}
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static int padlock_sha_export_nano(struct shash_desc *desc,
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void *out)
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{
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int statesize = crypto_shash_statesize(desc->tfm);
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void *sctx = shash_desc_ctx(desc);
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memcpy(out, sctx, statesize);
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return 0;
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}
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static int padlock_sha_import_nano(struct shash_desc *desc,
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const void *in)
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{
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int statesize = crypto_shash_statesize(desc->tfm);
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void *sctx = shash_desc_ctx(desc);
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memcpy(sctx, in, statesize);
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return 0;
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}
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static struct shash_alg sha1_alg_nano = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = padlock_sha1_init_nano,
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.update = padlock_sha1_update_nano,
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.final = padlock_sha1_final_nano,
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.export = padlock_sha_export_nano,
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.import = padlock_sha_import_nano,
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.descsize = sizeof(struct sha1_state),
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.statesize = sizeof(struct sha1_state),
|
|
.base = {
|
|
.cra_name = "sha1",
|
|
.cra_driver_name = "sha1-padlock-nano",
|
|
.cra_priority = PADLOCK_CRA_PRIORITY,
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
.cra_module = THIS_MODULE,
|
|
}
|
|
};
|
|
|
|
static struct shash_alg sha256_alg_nano = {
|
|
.digestsize = SHA256_DIGEST_SIZE,
|
|
.init = padlock_sha256_init_nano,
|
|
.update = padlock_sha256_update_nano,
|
|
.final = padlock_sha256_final_nano,
|
|
.export = padlock_sha_export_nano,
|
|
.import = padlock_sha_import_nano,
|
|
.descsize = sizeof(struct sha256_state),
|
|
.statesize = sizeof(struct sha256_state),
|
|
.base = {
|
|
.cra_name = "sha256",
|
|
.cra_driver_name = "sha256-padlock-nano",
|
|
.cra_priority = PADLOCK_CRA_PRIORITY,
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
|
.cra_module = THIS_MODULE,
|
|
}
|
|
};
|
|
|
|
static const struct x86_cpu_id padlock_sha_ids[] = {
|
|
X86_MATCH_FEATURE(X86_FEATURE_PHE, NULL),
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids);
|
|
|
|
static int __init padlock_init(void)
|
|
{
|
|
int rc = -ENODEV;
|
|
struct cpuinfo_x86 *c = &cpu_data(0);
|
|
struct shash_alg *sha1;
|
|
struct shash_alg *sha256;
|
|
|
|
if (!x86_match_cpu(padlock_sha_ids) || !boot_cpu_has(X86_FEATURE_PHE_EN))
|
|
return -ENODEV;
|
|
|
|
/* Register the newly added algorithm module if on *
|
|
* VIA Nano processor, or else just do as before */
|
|
if (c->x86_model < 0x0f) {
|
|
sha1 = &sha1_alg;
|
|
sha256 = &sha256_alg;
|
|
} else {
|
|
sha1 = &sha1_alg_nano;
|
|
sha256 = &sha256_alg_nano;
|
|
}
|
|
|
|
rc = crypto_register_shash(sha1);
|
|
if (rc)
|
|
goto out;
|
|
|
|
rc = crypto_register_shash(sha256);
|
|
if (rc)
|
|
goto out_unreg1;
|
|
|
|
printk(KERN_NOTICE PFX "Using VIA PadLock ACE for SHA1/SHA256 algorithms.\n");
|
|
|
|
return 0;
|
|
|
|
out_unreg1:
|
|
crypto_unregister_shash(sha1);
|
|
|
|
out:
|
|
printk(KERN_ERR PFX "VIA PadLock SHA1/SHA256 initialization failed.\n");
|
|
return rc;
|
|
}
|
|
|
|
static void __exit padlock_fini(void)
|
|
{
|
|
struct cpuinfo_x86 *c = &cpu_data(0);
|
|
|
|
if (c->x86_model >= 0x0f) {
|
|
crypto_unregister_shash(&sha1_alg_nano);
|
|
crypto_unregister_shash(&sha256_alg_nano);
|
|
} else {
|
|
crypto_unregister_shash(&sha1_alg);
|
|
crypto_unregister_shash(&sha256_alg);
|
|
}
|
|
}
|
|
|
|
module_init(padlock_init);
|
|
module_exit(padlock_fini);
|
|
|
|
MODULE_DESCRIPTION("VIA PadLock SHA1/SHA256 algorithms support.");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Michal Ludvig");
|
|
|
|
MODULE_ALIAS_CRYPTO("sha1-all");
|
|
MODULE_ALIAS_CRYPTO("sha256-all");
|
|
MODULE_ALIAS_CRYPTO("sha1-padlock");
|
|
MODULE_ALIAS_CRYPTO("sha256-padlock");
|