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![Russ Weight](/assets/img/avatar_default.png)
There is an error check following the allocation of flash_buf that returns
without freeing flash_buf. It makes more sense to do the error check
before the allocation and the reordering eliminates the memory leak.
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: 154afa5c31
("fpga: m10bmc-sec: expose max10 flash update count")
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Tom Rix <trix@redhat.com>
Acked-by: Xu Yilun <yilun.xu@intel.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220916235205.106873-1-russell.h.weight@intel.com
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
625 lines
16 KiB
C
625 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel MAX10 Board Management Controller Secure Update Driver
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*
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* Copyright (C) 2019-2022 Intel Corporation. All rights reserved.
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/device.h>
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#include <linux/firmware.h>
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#include <linux/mfd/intel-m10-bmc.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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struct m10bmc_sec {
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struct device *dev;
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struct intel_m10bmc *m10bmc;
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struct fw_upload *fwl;
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char *fw_name;
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u32 fw_name_id;
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bool cancel_request;
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};
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static DEFINE_XARRAY_ALLOC(fw_upload_xa);
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/* Root Entry Hash (REH) support */
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#define REH_SHA256_SIZE 32
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#define REH_SHA384_SIZE 48
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#define REH_MAGIC GENMASK(15, 0)
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#define REH_SHA_NUM_BYTES GENMASK(31, 16)
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static ssize_t
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show_root_entry_hash(struct device *dev, u32 exp_magic,
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u32 prog_addr, u32 reh_addr, char *buf)
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{
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struct m10bmc_sec *sec = dev_get_drvdata(dev);
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int sha_num_bytes, i, ret, cnt = 0;
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u8 hash[REH_SHA384_SIZE];
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unsigned int stride;
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u32 magic;
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stride = regmap_get_reg_stride(sec->m10bmc->regmap);
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ret = m10bmc_raw_read(sec->m10bmc, prog_addr, &magic);
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if (ret)
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return ret;
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if (FIELD_GET(REH_MAGIC, magic) != exp_magic)
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return sysfs_emit(buf, "hash not programmed\n");
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sha_num_bytes = FIELD_GET(REH_SHA_NUM_BYTES, magic) / 8;
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if ((sha_num_bytes % stride) ||
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(sha_num_bytes != REH_SHA256_SIZE &&
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sha_num_bytes != REH_SHA384_SIZE)) {
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dev_err(sec->dev, "%s bad sha num bytes %d\n", __func__,
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sha_num_bytes);
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return -EINVAL;
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}
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ret = regmap_bulk_read(sec->m10bmc->regmap, reh_addr,
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hash, sha_num_bytes / stride);
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if (ret) {
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dev_err(dev, "failed to read root entry hash: %x cnt %x: %d\n",
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reh_addr, sha_num_bytes / stride, ret);
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return ret;
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}
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for (i = 0; i < sha_num_bytes; i++)
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cnt += sprintf(buf + cnt, "%02x", hash[i]);
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cnt += sprintf(buf + cnt, "\n");
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return cnt;
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}
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#define DEVICE_ATTR_SEC_REH_RO(_name, _magic, _prog_addr, _reh_addr) \
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static ssize_t _name##_root_entry_hash_show(struct device *dev, \
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struct device_attribute *attr, \
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char *buf) \
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{ return show_root_entry_hash(dev, _magic, _prog_addr, _reh_addr, buf); } \
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static DEVICE_ATTR_RO(_name##_root_entry_hash)
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DEVICE_ATTR_SEC_REH_RO(bmc, BMC_PROG_MAGIC, BMC_PROG_ADDR, BMC_REH_ADDR);
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DEVICE_ATTR_SEC_REH_RO(sr, SR_PROG_MAGIC, SR_PROG_ADDR, SR_REH_ADDR);
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DEVICE_ATTR_SEC_REH_RO(pr, PR_PROG_MAGIC, PR_PROG_ADDR, PR_REH_ADDR);
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#define CSK_BIT_LEN 128U
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#define CSK_32ARRAY_SIZE DIV_ROUND_UP(CSK_BIT_LEN, 32)
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static ssize_t
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show_canceled_csk(struct device *dev, u32 addr, char *buf)
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{
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unsigned int i, stride, size = CSK_32ARRAY_SIZE * sizeof(u32);
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struct m10bmc_sec *sec = dev_get_drvdata(dev);
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DECLARE_BITMAP(csk_map, CSK_BIT_LEN);
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__le32 csk_le32[CSK_32ARRAY_SIZE];
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u32 csk32[CSK_32ARRAY_SIZE];
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int ret;
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stride = regmap_get_reg_stride(sec->m10bmc->regmap);
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if (size % stride) {
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dev_err(sec->dev,
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"CSK vector size (0x%x) not aligned to stride (0x%x)\n",
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size, stride);
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WARN_ON_ONCE(1);
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return -EINVAL;
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}
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ret = regmap_bulk_read(sec->m10bmc->regmap, addr, csk_le32,
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size / stride);
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if (ret) {
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dev_err(sec->dev, "failed to read CSK vector: %x cnt %x: %d\n",
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addr, size / stride, ret);
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return ret;
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}
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for (i = 0; i < CSK_32ARRAY_SIZE; i++)
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csk32[i] = le32_to_cpu(((csk_le32[i])));
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bitmap_from_arr32(csk_map, csk32, CSK_BIT_LEN);
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bitmap_complement(csk_map, csk_map, CSK_BIT_LEN);
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return bitmap_print_to_pagebuf(1, buf, csk_map, CSK_BIT_LEN);
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}
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#define DEVICE_ATTR_SEC_CSK_RO(_name, _addr) \
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static ssize_t _name##_canceled_csks_show(struct device *dev, \
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struct device_attribute *attr, \
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char *buf) \
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{ return show_canceled_csk(dev, _addr, buf); } \
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static DEVICE_ATTR_RO(_name##_canceled_csks)
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#define CSK_VEC_OFFSET 0x34
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DEVICE_ATTR_SEC_CSK_RO(bmc, BMC_PROG_ADDR + CSK_VEC_OFFSET);
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DEVICE_ATTR_SEC_CSK_RO(sr, SR_PROG_ADDR + CSK_VEC_OFFSET);
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DEVICE_ATTR_SEC_CSK_RO(pr, PR_PROG_ADDR + CSK_VEC_OFFSET);
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#define FLASH_COUNT_SIZE 4096 /* count stored as inverted bit vector */
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static ssize_t flash_count_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct m10bmc_sec *sec = dev_get_drvdata(dev);
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unsigned int stride, num_bits;
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u8 *flash_buf;
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int cnt, ret;
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stride = regmap_get_reg_stride(sec->m10bmc->regmap);
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num_bits = FLASH_COUNT_SIZE * 8;
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if (FLASH_COUNT_SIZE % stride) {
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dev_err(sec->dev,
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"FLASH_COUNT_SIZE (0x%x) not aligned to stride (0x%x)\n",
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FLASH_COUNT_SIZE, stride);
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WARN_ON_ONCE(1);
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return -EINVAL;
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}
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flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL);
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if (!flash_buf)
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return -ENOMEM;
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ret = regmap_bulk_read(sec->m10bmc->regmap, STAGING_FLASH_COUNT,
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flash_buf, FLASH_COUNT_SIZE / stride);
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if (ret) {
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dev_err(sec->dev,
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"failed to read flash count: %x cnt %x: %d\n",
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STAGING_FLASH_COUNT, FLASH_COUNT_SIZE / stride, ret);
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goto exit_free;
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}
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cnt = num_bits - bitmap_weight((unsigned long *)flash_buf, num_bits);
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exit_free:
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kfree(flash_buf);
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return ret ? : sysfs_emit(buf, "%u\n", cnt);
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}
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static DEVICE_ATTR_RO(flash_count);
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static struct attribute *m10bmc_security_attrs[] = {
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&dev_attr_flash_count.attr,
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&dev_attr_bmc_root_entry_hash.attr,
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&dev_attr_sr_root_entry_hash.attr,
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&dev_attr_pr_root_entry_hash.attr,
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&dev_attr_sr_canceled_csks.attr,
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&dev_attr_pr_canceled_csks.attr,
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&dev_attr_bmc_canceled_csks.attr,
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NULL,
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};
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static struct attribute_group m10bmc_security_attr_group = {
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.name = "security",
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.attrs = m10bmc_security_attrs,
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};
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static const struct attribute_group *m10bmc_sec_attr_groups[] = {
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&m10bmc_security_attr_group,
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NULL,
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};
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static void log_error_regs(struct m10bmc_sec *sec, u32 doorbell)
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{
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u32 auth_result;
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dev_err(sec->dev, "RSU error status: 0x%08x\n", doorbell);
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if (!m10bmc_sys_read(sec->m10bmc, M10BMC_AUTH_RESULT, &auth_result))
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dev_err(sec->dev, "RSU auth result: 0x%08x\n", auth_result);
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}
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static enum fw_upload_err rsu_check_idle(struct m10bmc_sec *sec)
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{
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u32 doorbell;
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int ret;
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ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell);
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if (ret)
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return FW_UPLOAD_ERR_RW_ERROR;
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if (rsu_prog(doorbell) != RSU_PROG_IDLE &&
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rsu_prog(doorbell) != RSU_PROG_RSU_DONE) {
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log_error_regs(sec, doorbell);
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return FW_UPLOAD_ERR_BUSY;
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}
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return FW_UPLOAD_ERR_NONE;
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}
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static inline bool rsu_start_done(u32 doorbell)
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{
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u32 status, progress;
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if (doorbell & DRBL_RSU_REQUEST)
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return false;
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status = rsu_stat(doorbell);
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if (status == RSU_STAT_ERASE_FAIL || status == RSU_STAT_WEAROUT)
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return true;
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progress = rsu_prog(doorbell);
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if (progress != RSU_PROG_IDLE && progress != RSU_PROG_RSU_DONE)
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return true;
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return false;
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}
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static enum fw_upload_err rsu_update_init(struct m10bmc_sec *sec)
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{
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u32 doorbell, status;
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int ret;
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ret = regmap_update_bits(sec->m10bmc->regmap,
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M10BMC_SYS_BASE + M10BMC_DOORBELL,
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DRBL_RSU_REQUEST | DRBL_HOST_STATUS,
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DRBL_RSU_REQUEST |
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FIELD_PREP(DRBL_HOST_STATUS,
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HOST_STATUS_IDLE));
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if (ret)
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return FW_UPLOAD_ERR_RW_ERROR;
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ret = regmap_read_poll_timeout(sec->m10bmc->regmap,
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M10BMC_SYS_BASE + M10BMC_DOORBELL,
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doorbell,
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rsu_start_done(doorbell),
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NIOS_HANDSHAKE_INTERVAL_US,
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NIOS_HANDSHAKE_TIMEOUT_US);
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if (ret == -ETIMEDOUT) {
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log_error_regs(sec, doorbell);
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return FW_UPLOAD_ERR_TIMEOUT;
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} else if (ret) {
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return FW_UPLOAD_ERR_RW_ERROR;
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}
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status = rsu_stat(doorbell);
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if (status == RSU_STAT_WEAROUT) {
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dev_warn(sec->dev, "Excessive flash update count detected\n");
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return FW_UPLOAD_ERR_WEAROUT;
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} else if (status == RSU_STAT_ERASE_FAIL) {
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log_error_regs(sec, doorbell);
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return FW_UPLOAD_ERR_HW_ERROR;
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}
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return FW_UPLOAD_ERR_NONE;
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}
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static enum fw_upload_err rsu_prog_ready(struct m10bmc_sec *sec)
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{
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unsigned long poll_timeout;
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u32 doorbell, progress;
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int ret;
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ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell);
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if (ret)
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return FW_UPLOAD_ERR_RW_ERROR;
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poll_timeout = jiffies + msecs_to_jiffies(RSU_PREP_TIMEOUT_MS);
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while (rsu_prog(doorbell) == RSU_PROG_PREPARE) {
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msleep(RSU_PREP_INTERVAL_MS);
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if (time_after(jiffies, poll_timeout))
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break;
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ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell);
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if (ret)
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return FW_UPLOAD_ERR_RW_ERROR;
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}
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progress = rsu_prog(doorbell);
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if (progress == RSU_PROG_PREPARE) {
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log_error_regs(sec, doorbell);
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return FW_UPLOAD_ERR_TIMEOUT;
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} else if (progress != RSU_PROG_READY) {
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log_error_regs(sec, doorbell);
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return FW_UPLOAD_ERR_HW_ERROR;
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}
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return FW_UPLOAD_ERR_NONE;
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}
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static enum fw_upload_err rsu_send_data(struct m10bmc_sec *sec)
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{
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u32 doorbell;
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int ret;
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ret = regmap_update_bits(sec->m10bmc->regmap,
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M10BMC_SYS_BASE + M10BMC_DOORBELL,
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DRBL_HOST_STATUS,
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FIELD_PREP(DRBL_HOST_STATUS,
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HOST_STATUS_WRITE_DONE));
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if (ret)
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return FW_UPLOAD_ERR_RW_ERROR;
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ret = regmap_read_poll_timeout(sec->m10bmc->regmap,
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M10BMC_SYS_BASE + M10BMC_DOORBELL,
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doorbell,
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rsu_prog(doorbell) != RSU_PROG_READY,
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NIOS_HANDSHAKE_INTERVAL_US,
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NIOS_HANDSHAKE_TIMEOUT_US);
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if (ret == -ETIMEDOUT) {
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log_error_regs(sec, doorbell);
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return FW_UPLOAD_ERR_TIMEOUT;
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} else if (ret) {
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return FW_UPLOAD_ERR_RW_ERROR;
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}
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switch (rsu_stat(doorbell)) {
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case RSU_STAT_NORMAL:
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case RSU_STAT_NIOS_OK:
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case RSU_STAT_USER_OK:
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case RSU_STAT_FACTORY_OK:
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break;
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default:
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log_error_regs(sec, doorbell);
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return FW_UPLOAD_ERR_HW_ERROR;
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}
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return FW_UPLOAD_ERR_NONE;
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}
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static int rsu_check_complete(struct m10bmc_sec *sec, u32 *doorbell)
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{
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if (m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, doorbell))
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return -EIO;
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switch (rsu_stat(*doorbell)) {
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case RSU_STAT_NORMAL:
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case RSU_STAT_NIOS_OK:
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case RSU_STAT_USER_OK:
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case RSU_STAT_FACTORY_OK:
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break;
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default:
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return -EINVAL;
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}
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switch (rsu_prog(*doorbell)) {
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case RSU_PROG_IDLE:
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case RSU_PROG_RSU_DONE:
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return 0;
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case RSU_PROG_AUTHENTICATING:
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case RSU_PROG_COPYING:
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case RSU_PROG_UPDATE_CANCEL:
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case RSU_PROG_PROGRAM_KEY_HASH:
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return -EAGAIN;
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default:
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return -EINVAL;
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}
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}
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static enum fw_upload_err rsu_cancel(struct m10bmc_sec *sec)
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{
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u32 doorbell;
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int ret;
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ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell);
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if (ret)
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return FW_UPLOAD_ERR_RW_ERROR;
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if (rsu_prog(doorbell) != RSU_PROG_READY)
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return FW_UPLOAD_ERR_BUSY;
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ret = regmap_update_bits(sec->m10bmc->regmap,
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M10BMC_SYS_BASE + M10BMC_DOORBELL,
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DRBL_HOST_STATUS,
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FIELD_PREP(DRBL_HOST_STATUS,
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HOST_STATUS_ABORT_RSU));
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if (ret)
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return FW_UPLOAD_ERR_RW_ERROR;
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return FW_UPLOAD_ERR_CANCELED;
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}
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static enum fw_upload_err m10bmc_sec_prepare(struct fw_upload *fwl,
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const u8 *data, u32 size)
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{
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struct m10bmc_sec *sec = fwl->dd_handle;
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u32 ret;
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sec->cancel_request = false;
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if (!size || size > M10BMC_STAGING_SIZE)
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return FW_UPLOAD_ERR_INVALID_SIZE;
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ret = rsu_check_idle(sec);
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if (ret != FW_UPLOAD_ERR_NONE)
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return ret;
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ret = rsu_update_init(sec);
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if (ret != FW_UPLOAD_ERR_NONE)
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return ret;
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ret = rsu_prog_ready(sec);
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if (ret != FW_UPLOAD_ERR_NONE)
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return ret;
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if (sec->cancel_request)
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return rsu_cancel(sec);
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return FW_UPLOAD_ERR_NONE;
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}
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#define WRITE_BLOCK_SIZE 0x4000 /* Default write-block size is 0x4000 bytes */
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static enum fw_upload_err m10bmc_sec_write(struct fw_upload *fwl, const u8 *data,
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u32 offset, u32 size, u32 *written)
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{
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struct m10bmc_sec *sec = fwl->dd_handle;
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u32 blk_size, doorbell, extra_offset;
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unsigned int stride, extra = 0;
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int ret;
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stride = regmap_get_reg_stride(sec->m10bmc->regmap);
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if (sec->cancel_request)
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return rsu_cancel(sec);
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|
|
ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell);
|
|
if (ret) {
|
|
return FW_UPLOAD_ERR_RW_ERROR;
|
|
} else if (rsu_prog(doorbell) != RSU_PROG_READY) {
|
|
log_error_regs(sec, doorbell);
|
|
return FW_UPLOAD_ERR_HW_ERROR;
|
|
}
|
|
|
|
WARN_ON_ONCE(WRITE_BLOCK_SIZE % stride);
|
|
blk_size = min_t(u32, WRITE_BLOCK_SIZE, size);
|
|
ret = regmap_bulk_write(sec->m10bmc->regmap,
|
|
M10BMC_STAGING_BASE + offset,
|
|
(void *)data + offset,
|
|
blk_size / stride);
|
|
if (ret)
|
|
return FW_UPLOAD_ERR_RW_ERROR;
|
|
|
|
/*
|
|
* If blk_size is not aligned to stride, then handle the extra
|
|
* bytes with regmap_write.
|
|
*/
|
|
if (blk_size % stride) {
|
|
extra_offset = offset + ALIGN_DOWN(blk_size, stride);
|
|
memcpy(&extra, (u8 *)(data + extra_offset), blk_size % stride);
|
|
ret = regmap_write(sec->m10bmc->regmap,
|
|
M10BMC_STAGING_BASE + extra_offset, extra);
|
|
if (ret)
|
|
return FW_UPLOAD_ERR_RW_ERROR;
|
|
}
|
|
|
|
*written = blk_size;
|
|
return FW_UPLOAD_ERR_NONE;
|
|
}
|
|
|
|
static enum fw_upload_err m10bmc_sec_poll_complete(struct fw_upload *fwl)
|
|
{
|
|
struct m10bmc_sec *sec = fwl->dd_handle;
|
|
unsigned long poll_timeout;
|
|
u32 doorbell, result;
|
|
int ret;
|
|
|
|
if (sec->cancel_request)
|
|
return rsu_cancel(sec);
|
|
|
|
result = rsu_send_data(sec);
|
|
if (result != FW_UPLOAD_ERR_NONE)
|
|
return result;
|
|
|
|
poll_timeout = jiffies + msecs_to_jiffies(RSU_COMPLETE_TIMEOUT_MS);
|
|
do {
|
|
msleep(RSU_COMPLETE_INTERVAL_MS);
|
|
ret = rsu_check_complete(sec, &doorbell);
|
|
} while (ret == -EAGAIN && !time_after(jiffies, poll_timeout));
|
|
|
|
if (ret == -EAGAIN) {
|
|
log_error_regs(sec, doorbell);
|
|
return FW_UPLOAD_ERR_TIMEOUT;
|
|
} else if (ret == -EIO) {
|
|
return FW_UPLOAD_ERR_RW_ERROR;
|
|
} else if (ret) {
|
|
log_error_regs(sec, doorbell);
|
|
return FW_UPLOAD_ERR_HW_ERROR;
|
|
}
|
|
|
|
return FW_UPLOAD_ERR_NONE;
|
|
}
|
|
|
|
/*
|
|
* m10bmc_sec_cancel() may be called asynchronously with an on-going update.
|
|
* All other functions are called sequentially in a single thread. To avoid
|
|
* contention on register accesses, m10bmc_sec_cancel() must only update
|
|
* the cancel_request flag. Other functions will check this flag and handle
|
|
* the cancel request synchronously.
|
|
*/
|
|
static void m10bmc_sec_cancel(struct fw_upload *fwl)
|
|
{
|
|
struct m10bmc_sec *sec = fwl->dd_handle;
|
|
|
|
sec->cancel_request = true;
|
|
}
|
|
|
|
static void m10bmc_sec_cleanup(struct fw_upload *fwl)
|
|
{
|
|
struct m10bmc_sec *sec = fwl->dd_handle;
|
|
|
|
(void)rsu_cancel(sec);
|
|
}
|
|
|
|
static const struct fw_upload_ops m10bmc_ops = {
|
|
.prepare = m10bmc_sec_prepare,
|
|
.write = m10bmc_sec_write,
|
|
.poll_complete = m10bmc_sec_poll_complete,
|
|
.cancel = m10bmc_sec_cancel,
|
|
.cleanup = m10bmc_sec_cleanup,
|
|
};
|
|
|
|
#define SEC_UPDATE_LEN_MAX 32
|
|
static int m10bmc_sec_probe(struct platform_device *pdev)
|
|
{
|
|
char buf[SEC_UPDATE_LEN_MAX];
|
|
struct m10bmc_sec *sec;
|
|
struct fw_upload *fwl;
|
|
unsigned int len;
|
|
int ret;
|
|
|
|
sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);
|
|
if (!sec)
|
|
return -ENOMEM;
|
|
|
|
sec->dev = &pdev->dev;
|
|
sec->m10bmc = dev_get_drvdata(pdev->dev.parent);
|
|
dev_set_drvdata(&pdev->dev, sec);
|
|
|
|
ret = xa_alloc(&fw_upload_xa, &sec->fw_name_id, sec,
|
|
xa_limit_32b, GFP_KERNEL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
len = scnprintf(buf, SEC_UPDATE_LEN_MAX, "secure-update%d",
|
|
sec->fw_name_id);
|
|
sec->fw_name = kmemdup_nul(buf, len, GFP_KERNEL);
|
|
if (!sec->fw_name)
|
|
return -ENOMEM;
|
|
|
|
fwl = firmware_upload_register(THIS_MODULE, sec->dev, sec->fw_name,
|
|
&m10bmc_ops, sec);
|
|
if (IS_ERR(fwl)) {
|
|
dev_err(sec->dev, "Firmware Upload driver failed to start\n");
|
|
kfree(sec->fw_name);
|
|
xa_erase(&fw_upload_xa, sec->fw_name_id);
|
|
return PTR_ERR(fwl);
|
|
}
|
|
|
|
sec->fwl = fwl;
|
|
return 0;
|
|
}
|
|
|
|
static int m10bmc_sec_remove(struct platform_device *pdev)
|
|
{
|
|
struct m10bmc_sec *sec = dev_get_drvdata(&pdev->dev);
|
|
|
|
firmware_upload_unregister(sec->fwl);
|
|
kfree(sec->fw_name);
|
|
xa_erase(&fw_upload_xa, sec->fw_name_id);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_device_id intel_m10bmc_sec_ids[] = {
|
|
{
|
|
.name = "n3000bmc-sec-update",
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, intel_m10bmc_sec_ids);
|
|
|
|
static struct platform_driver intel_m10bmc_sec_driver = {
|
|
.probe = m10bmc_sec_probe,
|
|
.remove = m10bmc_sec_remove,
|
|
.driver = {
|
|
.name = "intel-m10bmc-sec-update",
|
|
.dev_groups = m10bmc_sec_attr_groups,
|
|
},
|
|
.id_table = intel_m10bmc_sec_ids,
|
|
};
|
|
module_platform_driver(intel_m10bmc_sec_driver);
|
|
|
|
MODULE_AUTHOR("Intel Corporation");
|
|
MODULE_DESCRIPTION("Intel MAX10 BMC Secure Update");
|
|
MODULE_LICENSE("GPL");
|