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![Andy Shevchenko](/assets/img/avatar_default.png)
There are a few of spelling issues in the comment, fix them. While at it, fix indentation in the MODULE_AUTHOR() parameter and update copyright years. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220628221747.33956-11-andriy.shevchenko@linux.intel.com
585 lines
14 KiB
C
585 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MFD core driver for Intel Broxton Whiskey Cove PMIC
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*
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* Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved.
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*/
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#include <linux/acpi.h>
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#include <linux/bits.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/mfd/intel_soc_pmic_bxtwc.h>
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#include <linux/module.h>
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#include <asm/intel_scu_ipc.h>
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/* PMIC device registers */
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#define REG_ADDR_MASK GENMASK(15, 8)
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#define REG_ADDR_SHIFT 8
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#define REG_OFFSET_MASK GENMASK(7, 0)
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/* Interrupt Status Registers */
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#define BXTWC_IRQLVL1 0x4E02
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#define BXTWC_PWRBTNIRQ 0x4E03
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#define BXTWC_THRM0IRQ 0x4E04
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#define BXTWC_THRM1IRQ 0x4E05
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#define BXTWC_THRM2IRQ 0x4E06
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#define BXTWC_BCUIRQ 0x4E07
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#define BXTWC_ADCIRQ 0x4E08
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#define BXTWC_CHGR0IRQ 0x4E09
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#define BXTWC_CHGR1IRQ 0x4E0A
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#define BXTWC_GPIOIRQ0 0x4E0B
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#define BXTWC_GPIOIRQ1 0x4E0C
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#define BXTWC_CRITIRQ 0x4E0D
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#define BXTWC_TMUIRQ 0x4FB6
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/* Interrupt MASK Registers */
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#define BXTWC_MIRQLVL1 0x4E0E
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#define BXTWC_MIRQLVL1_MCHGR BIT(5)
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#define BXTWC_MPWRBTNIRQ 0x4E0F
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#define BXTWC_MTHRM0IRQ 0x4E12
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#define BXTWC_MTHRM1IRQ 0x4E13
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#define BXTWC_MTHRM2IRQ 0x4E14
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#define BXTWC_MBCUIRQ 0x4E15
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#define BXTWC_MADCIRQ 0x4E16
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#define BXTWC_MCHGR0IRQ 0x4E17
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#define BXTWC_MCHGR1IRQ 0x4E18
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#define BXTWC_MGPIO0IRQ 0x4E19
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#define BXTWC_MGPIO1IRQ 0x4E1A
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#define BXTWC_MCRITIRQ 0x4E1B
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#define BXTWC_MTMUIRQ 0x4FB7
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/* Whiskey Cove PMIC share same ACPI ID between different platforms */
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#define BROXTON_PMIC_WC_HRV 4
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#define PMC_PMIC_ACCESS 0xFF
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#define PMC_PMIC_READ 0x0
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#define PMC_PMIC_WRITE 0x1
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enum bxtwc_irqs {
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BXTWC_PWRBTN_LVL1_IRQ = 0,
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BXTWC_TMU_LVL1_IRQ,
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BXTWC_THRM_LVL1_IRQ,
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BXTWC_BCU_LVL1_IRQ,
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BXTWC_ADC_LVL1_IRQ,
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BXTWC_CHGR_LVL1_IRQ,
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BXTWC_GPIO_LVL1_IRQ,
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BXTWC_CRIT_LVL1_IRQ,
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};
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enum bxtwc_irqs_pwrbtn {
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BXTWC_PWRBTN_IRQ = 0,
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BXTWC_UIBTN_IRQ,
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};
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enum bxtwc_irqs_bcu {
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BXTWC_BCU_IRQ = 0,
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};
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enum bxtwc_irqs_adc {
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BXTWC_ADC_IRQ = 0,
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};
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enum bxtwc_irqs_chgr {
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BXTWC_USBC_IRQ = 0,
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BXTWC_CHGR0_IRQ,
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BXTWC_CHGR1_IRQ,
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};
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enum bxtwc_irqs_tmu {
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BXTWC_TMU_IRQ = 0,
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};
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enum bxtwc_irqs_crit {
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BXTWC_CRIT_IRQ = 0,
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};
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static const struct regmap_irq bxtwc_regmap_irqs[] = {
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REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
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REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
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REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
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REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
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REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
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REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
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REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
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REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
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};
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static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = {
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REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, BIT(0)),
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};
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static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
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REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, GENMASK(4, 0)),
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};
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static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
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REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, GENMASK(7, 0)),
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};
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static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
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REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
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REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, GENMASK(4, 0)),
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REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, GENMASK(4, 0)),
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};
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static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
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REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, GENMASK(2, 1)),
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};
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static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
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REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, GENMASK(1, 0)),
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};
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static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
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.name = "bxtwc_irq_chip",
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.status_base = BXTWC_IRQLVL1,
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.mask_base = BXTWC_MIRQLVL1,
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.irqs = bxtwc_regmap_irqs,
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.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
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.num_regs = 1,
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};
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static struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {
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.name = "bxtwc_irq_chip_pwrbtn",
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.status_base = BXTWC_PWRBTNIRQ,
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.mask_base = BXTWC_MPWRBTNIRQ,
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.irqs = bxtwc_regmap_irqs_pwrbtn,
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.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_pwrbtn),
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.num_regs = 1,
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};
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static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
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.name = "bxtwc_irq_chip_tmu",
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.status_base = BXTWC_TMUIRQ,
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.mask_base = BXTWC_MTMUIRQ,
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.irqs = bxtwc_regmap_irqs_tmu,
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.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
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.num_regs = 1,
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};
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static struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
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.name = "bxtwc_irq_chip_bcu",
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.status_base = BXTWC_BCUIRQ,
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.mask_base = BXTWC_MBCUIRQ,
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.irqs = bxtwc_regmap_irqs_bcu,
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.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),
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.num_regs = 1,
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};
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static struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
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.name = "bxtwc_irq_chip_adc",
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.status_base = BXTWC_ADCIRQ,
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.mask_base = BXTWC_MADCIRQ,
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.irqs = bxtwc_regmap_irqs_adc,
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.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),
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.num_regs = 1,
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};
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static struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
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.name = "bxtwc_irq_chip_chgr",
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.status_base = BXTWC_CHGR0IRQ,
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.mask_base = BXTWC_MCHGR0IRQ,
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.irqs = bxtwc_regmap_irqs_chgr,
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.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),
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.num_regs = 2,
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};
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static struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
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.name = "bxtwc_irq_chip_crit",
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.status_base = BXTWC_CRITIRQ,
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.mask_base = BXTWC_MCRITIRQ,
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.irqs = bxtwc_regmap_irqs_crit,
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.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),
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.num_regs = 1,
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};
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static const struct resource gpio_resources[] = {
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DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
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};
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static const struct resource adc_resources[] = {
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DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
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};
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static const struct resource usbc_resources[] = {
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DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
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};
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static const struct resource charger_resources[] = {
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DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
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DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
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};
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static const struct resource thermal_resources[] = {
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DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
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};
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static const struct resource bcu_resources[] = {
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DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
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};
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static const struct resource tmu_resources[] = {
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DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
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};
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static struct mfd_cell bxt_wc_dev[] = {
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{
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.name = "bxt_wcove_gpadc",
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.num_resources = ARRAY_SIZE(adc_resources),
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.resources = adc_resources,
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},
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{
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.name = "bxt_wcove_thermal",
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.num_resources = ARRAY_SIZE(thermal_resources),
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.resources = thermal_resources,
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},
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{
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.name = "bxt_wcove_usbc",
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.num_resources = ARRAY_SIZE(usbc_resources),
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.resources = usbc_resources,
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},
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{
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.name = "bxt_wcove_ext_charger",
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.num_resources = ARRAY_SIZE(charger_resources),
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.resources = charger_resources,
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},
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{
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.name = "bxt_wcove_bcu",
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.num_resources = ARRAY_SIZE(bcu_resources),
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.resources = bcu_resources,
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},
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{
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.name = "bxt_wcove_tmu",
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.num_resources = ARRAY_SIZE(tmu_resources),
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.resources = tmu_resources,
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},
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{
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.name = "bxt_wcove_gpio",
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resources = gpio_resources,
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},
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{
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.name = "bxt_wcove_region",
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},
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};
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static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
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unsigned int *val)
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{
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int ret;
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int i2c_addr;
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u8 ipc_in[2];
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u8 ipc_out[4];
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struct intel_soc_pmic *pmic = context;
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if (!pmic)
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return -EINVAL;
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if (reg & REG_ADDR_MASK)
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i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
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else
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i2c_addr = BXTWC_DEVICE1_ADDR;
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reg &= REG_OFFSET_MASK;
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ipc_in[0] = reg;
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ipc_in[1] = i2c_addr;
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ret = intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS,
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PMC_PMIC_READ, ipc_in, sizeof(ipc_in),
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ipc_out, sizeof(ipc_out));
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if (ret)
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return ret;
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*val = ipc_out[0];
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return 0;
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}
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static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
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unsigned int val)
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{
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int i2c_addr;
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u8 ipc_in[3];
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struct intel_soc_pmic *pmic = context;
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if (!pmic)
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return -EINVAL;
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if (reg & REG_ADDR_MASK)
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i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
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else
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i2c_addr = BXTWC_DEVICE1_ADDR;
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reg &= REG_OFFSET_MASK;
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ipc_in[0] = reg;
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ipc_in[1] = i2c_addr;
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ipc_in[2] = val;
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return intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS,
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PMC_PMIC_WRITE, ipc_in, sizeof(ipc_in),
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NULL, 0);
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}
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/* sysfs interfaces to r/w PMIC registers, required by initial script */
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static unsigned long bxtwc_reg_addr;
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static ssize_t addr_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sysfs_emit(buf, "0x%lx\n", bxtwc_reg_addr);
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}
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static ssize_t addr_store(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count)
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{
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int ret;
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ret = kstrtoul(buf, 0, &bxtwc_reg_addr);
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if (ret)
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return ret;
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return count;
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}
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static ssize_t val_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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int ret;
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unsigned int val;
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
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if (ret) {
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dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
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return ret;
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}
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return sysfs_emit(buf, "0x%02x\n", val);
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}
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static ssize_t val_store(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count)
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{
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int ret;
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unsigned int val;
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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ret = kstrtouint(buf, 0, &val);
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if (ret)
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return ret;
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ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
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if (ret) {
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dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
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val, bxtwc_reg_addr);
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return ret;
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}
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return count;
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}
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static DEVICE_ATTR_ADMIN_RW(addr);
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static DEVICE_ATTR_ADMIN_RW(val);
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static struct attribute *bxtwc_attrs[] = {
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&dev_attr_addr.attr,
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&dev_attr_val.attr,
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NULL
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};
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static const struct attribute_group bxtwc_group = {
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.attrs = bxtwc_attrs,
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};
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static const struct attribute_group *bxtwc_groups[] = {
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&bxtwc_group,
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NULL
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};
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static const struct regmap_config bxtwc_regmap_config = {
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.reg_bits = 16,
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.val_bits = 8,
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.reg_write = regmap_ipc_byte_reg_write,
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.reg_read = regmap_ipc_byte_reg_read,
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};
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static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
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struct regmap_irq_chip_data *pdata,
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int pirq, int irq_flags,
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const struct regmap_irq_chip *chip,
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struct regmap_irq_chip_data **data)
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{
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int irq;
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irq = regmap_irq_get_virq(pdata, pirq);
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if (irq < 0)
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return dev_err_probe(pmic->dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",
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pirq, chip->name);
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return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
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0, chip, data);
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}
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static int bxtwc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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int ret;
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acpi_status status;
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unsigned long long hrv;
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struct intel_soc_pmic *pmic;
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status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
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if (ACPI_FAILURE(status))
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return dev_err_probe(dev, -ENODEV, "Failed to get PMIC hardware revision\n");
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if (hrv != BROXTON_PMIC_WC_HRV)
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return dev_err_probe(dev, -ENODEV, "Invalid PMIC hardware revision: %llu\n", hrv);
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pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
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if (!pmic)
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return -ENOMEM;
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ret = platform_get_irq(pdev, 0);
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if (ret < 0)
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return ret;
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pmic->irq = ret;
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platform_set_drvdata(pdev, pmic);
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pmic->dev = dev;
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pmic->scu = devm_intel_scu_ipc_dev_get(dev);
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if (!pmic->scu)
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return -EPROBE_DEFER;
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pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bxtwc_regmap_config);
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if (IS_ERR(pmic->regmap))
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return dev_err_probe(dev, PTR_ERR(pmic->regmap), "Failed to initialise regmap\n");
|
|
|
|
ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
|
|
IRQF_ONESHOT | IRQF_SHARED,
|
|
0, &bxtwc_regmap_irq_chip,
|
|
&pmic->irq_chip_data);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Failed to add IRQ chip\n");
|
|
|
|
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
|
|
BXTWC_PWRBTN_LVL1_IRQ,
|
|
IRQF_ONESHOT,
|
|
&bxtwc_regmap_irq_chip_pwrbtn,
|
|
&pmic->irq_chip_data_pwrbtn);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Failed to add PWRBTN IRQ chip\n");
|
|
|
|
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
|
|
BXTWC_TMU_LVL1_IRQ,
|
|
IRQF_ONESHOT,
|
|
&bxtwc_regmap_irq_chip_tmu,
|
|
&pmic->irq_chip_data_tmu);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Failed to add TMU IRQ chip\n");
|
|
|
|
/* Add chained IRQ handler for BCU IRQs */
|
|
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
|
|
BXTWC_BCU_LVL1_IRQ,
|
|
IRQF_ONESHOT,
|
|
&bxtwc_regmap_irq_chip_bcu,
|
|
&pmic->irq_chip_data_bcu);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Failed to add BUC IRQ chip\n");
|
|
|
|
/* Add chained IRQ handler for ADC IRQs */
|
|
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
|
|
BXTWC_ADC_LVL1_IRQ,
|
|
IRQF_ONESHOT,
|
|
&bxtwc_regmap_irq_chip_adc,
|
|
&pmic->irq_chip_data_adc);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Failed to add ADC IRQ chip\n");
|
|
|
|
/* Add chained IRQ handler for CHGR IRQs */
|
|
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
|
|
BXTWC_CHGR_LVL1_IRQ,
|
|
IRQF_ONESHOT,
|
|
&bxtwc_regmap_irq_chip_chgr,
|
|
&pmic->irq_chip_data_chgr);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Failed to add CHGR IRQ chip\n");
|
|
|
|
/* Add chained IRQ handler for CRIT IRQs */
|
|
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
|
|
BXTWC_CRIT_LVL1_IRQ,
|
|
IRQF_ONESHOT,
|
|
&bxtwc_regmap_irq_chip_crit,
|
|
&pmic->irq_chip_data_crit);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Failed to add CRIT IRQ chip\n");
|
|
|
|
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, bxt_wc_dev, ARRAY_SIZE(bxt_wc_dev),
|
|
NULL, 0, NULL);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Failed to add devices\n");
|
|
|
|
/*
|
|
* There is a known H/W bug. Upon reset, BIT 5 of register
|
|
* BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
|
|
* later it's set to 1(masked) automatically by hardware. So we
|
|
* place the software workaround here to unmask it again in order
|
|
* to re-enable the charger interrupt.
|
|
*/
|
|
regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1, BXTWC_MIRQLVL1_MCHGR, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void bxtwc_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct intel_soc_pmic *pmic = platform_get_drvdata(pdev);
|
|
|
|
disable_irq(pmic->irq);
|
|
}
|
|
|
|
static int bxtwc_suspend(struct device *dev)
|
|
{
|
|
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
|
|
|
|
disable_irq(pmic->irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bxtwc_resume(struct device *dev)
|
|
{
|
|
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
|
|
|
|
enable_irq(pmic->irq);
|
|
return 0;
|
|
}
|
|
|
|
static DEFINE_SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
|
|
|
|
static const struct acpi_device_id bxtwc_acpi_ids[] = {
|
|
{ "INT34D3", },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);
|
|
|
|
static struct platform_driver bxtwc_driver = {
|
|
.probe = bxtwc_probe,
|
|
.shutdown = bxtwc_shutdown,
|
|
.driver = {
|
|
.name = "BXTWC PMIC",
|
|
.pm = pm_sleep_ptr(&bxtwc_pm_ops),
|
|
.acpi_match_table = bxtwc_acpi_ids,
|
|
.dev_groups = bxtwc_groups,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(bxtwc_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Qipeng Zha <qipeng.zha@intel.com>");
|