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![Heiner Kallweit](/assets/img/avatar_default.png)
Use new function pci_read_vpd_any() to simplify the code. [bhelgaas: squash in fix for stack overflow reported & tested by Qian [1] and Kunihiko [2]: [1] https://lore.kernel.org/netdev/e89087c5-c495-c5ca-feb1-54cf3a8775c5@quicinc.com/ [2] https://lore.kernel.org/r/2f7e3770-ab47-42b5-719c-f7c661c07d28@socionext.com Link: https://lore.kernel.org/r/6211be8a-5d10-8f3a-6d33-af695dc35caf@gmail.com Reported-by: Qian Cai <quic_qiancai@quicinc.com> Tested-by: Qian Cai <quic_qiancai@quicinc.com> Reported-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Tested-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> ] Link: https://lore.kernel.org/r/049fa71c-c7af-9c69-51c0-05c1bc2bf660@gmail.com Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jakub Kicinski <kuba@kernel.org>
596 lines
15 KiB
C
596 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCI VPD support
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*
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* Copyright (C) 2010 Broadcom Corporation.
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*/
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/sched/signal.h>
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#include <asm/unaligned.h>
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#include "pci.h"
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#define PCI_VPD_LRDT_TAG_SIZE 3
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#define PCI_VPD_SRDT_LEN_MASK 0x07
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#define PCI_VPD_SRDT_TAG_SIZE 1
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#define PCI_VPD_STIN_END 0x0f
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#define PCI_VPD_INFO_FLD_HDR_SIZE 3
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static u16 pci_vpd_lrdt_size(const u8 *lrdt)
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{
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return get_unaligned_le16(lrdt + 1);
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}
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static u8 pci_vpd_srdt_tag(const u8 *srdt)
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{
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return *srdt >> 3;
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}
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static u8 pci_vpd_srdt_size(const u8 *srdt)
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{
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return *srdt & PCI_VPD_SRDT_LEN_MASK;
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}
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static u8 pci_vpd_info_field_size(const u8 *info_field)
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{
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return info_field[2];
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}
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/* VPD access through PCI 2.2+ VPD capability */
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static struct pci_dev *pci_get_func0_dev(struct pci_dev *dev)
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{
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return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
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}
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#define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
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#define PCI_VPD_SZ_INVALID UINT_MAX
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/**
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* pci_vpd_size - determine actual size of Vital Product Data
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* @dev: pci device struct
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*/
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static size_t pci_vpd_size(struct pci_dev *dev)
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{
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size_t off = 0, size;
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unsigned char tag, header[1+2]; /* 1 byte tag, 2 bytes length */
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while (pci_read_vpd_any(dev, off, 1, header) == 1) {
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size = 0;
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if (off == 0 && (header[0] == 0x00 || header[0] == 0xff))
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goto error;
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if (header[0] & PCI_VPD_LRDT) {
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/* Large Resource Data Type Tag */
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if (pci_read_vpd_any(dev, off + 1, 2, &header[1]) != 2) {
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pci_warn(dev, "failed VPD read at offset %zu\n",
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off + 1);
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return off ?: PCI_VPD_SZ_INVALID;
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}
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size = pci_vpd_lrdt_size(header);
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if (off + size > PCI_VPD_MAX_SIZE)
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goto error;
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off += PCI_VPD_LRDT_TAG_SIZE + size;
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} else {
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/* Short Resource Data Type Tag */
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tag = pci_vpd_srdt_tag(header);
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size = pci_vpd_srdt_size(header);
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if (off + size > PCI_VPD_MAX_SIZE)
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goto error;
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off += PCI_VPD_SRDT_TAG_SIZE + size;
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if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
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return off;
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}
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}
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return off;
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error:
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pci_info(dev, "invalid VPD tag %#04x (size %zu) at offset %zu%s\n",
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header[0], size, off, off == 0 ?
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"; assume missing optional EEPROM" : "");
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return off ?: PCI_VPD_SZ_INVALID;
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}
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static bool pci_vpd_available(struct pci_dev *dev, bool check_size)
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{
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struct pci_vpd *vpd = &dev->vpd;
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if (!vpd->cap)
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return false;
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if (vpd->len == 0 && check_size) {
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vpd->len = pci_vpd_size(dev);
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if (vpd->len == PCI_VPD_SZ_INVALID) {
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vpd->cap = 0;
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return false;
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}
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}
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return true;
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}
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/*
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* Wait for last operation to complete.
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* This code has to spin since there is no other notification from the PCI
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* hardware. Since the VPD is often implemented by serial attachment to an
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* EEPROM, it may take many milliseconds to complete.
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* @set: if true wait for flag to be set, else wait for it to be cleared
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*
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* Returns 0 on success, negative values indicate error.
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*/
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static int pci_vpd_wait(struct pci_dev *dev, bool set)
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{
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struct pci_vpd *vpd = &dev->vpd;
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unsigned long timeout = jiffies + msecs_to_jiffies(125);
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unsigned long max_sleep = 16;
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u16 status;
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int ret;
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do {
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ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
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&status);
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if (ret < 0)
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return ret;
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if (!!(status & PCI_VPD_ADDR_F) == set)
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return 0;
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if (time_after(jiffies, timeout))
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break;
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usleep_range(10, max_sleep);
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if (max_sleep < 1024)
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max_sleep *= 2;
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} while (true);
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pci_warn(dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
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return -ETIMEDOUT;
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}
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static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
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void *arg, bool check_size)
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{
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struct pci_vpd *vpd = &dev->vpd;
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unsigned int max_len;
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int ret = 0;
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loff_t end = pos + count;
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u8 *buf = arg;
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if (!pci_vpd_available(dev, check_size))
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return -ENODEV;
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if (pos < 0)
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return -EINVAL;
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max_len = check_size ? vpd->len : PCI_VPD_MAX_SIZE;
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if (pos >= max_len)
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return 0;
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if (end > max_len) {
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end = max_len;
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count = end - pos;
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}
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if (mutex_lock_killable(&vpd->lock))
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return -EINTR;
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while (pos < end) {
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u32 val;
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unsigned int i, skip;
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if (fatal_signal_pending(current)) {
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ret = -EINTR;
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break;
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}
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ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
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pos & ~3);
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if (ret < 0)
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break;
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ret = pci_vpd_wait(dev, true);
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if (ret < 0)
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break;
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ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
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if (ret < 0)
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break;
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skip = pos & 3;
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for (i = 0; i < sizeof(u32); i++) {
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if (i >= skip) {
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*buf++ = val;
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if (++pos == end)
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break;
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}
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val >>= 8;
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}
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}
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mutex_unlock(&vpd->lock);
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return ret ? ret : count;
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}
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static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
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const void *arg, bool check_size)
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{
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struct pci_vpd *vpd = &dev->vpd;
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unsigned int max_len;
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const u8 *buf = arg;
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loff_t end = pos + count;
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int ret = 0;
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if (!pci_vpd_available(dev, check_size))
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return -ENODEV;
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if (pos < 0 || (pos & 3) || (count & 3))
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return -EINVAL;
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max_len = check_size ? vpd->len : PCI_VPD_MAX_SIZE;
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if (end > max_len)
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return -EINVAL;
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if (mutex_lock_killable(&vpd->lock))
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return -EINTR;
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while (pos < end) {
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ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA,
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get_unaligned_le32(buf));
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if (ret < 0)
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break;
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ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
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pos | PCI_VPD_ADDR_F);
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if (ret < 0)
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break;
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ret = pci_vpd_wait(dev, false);
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if (ret < 0)
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break;
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buf += sizeof(u32);
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pos += sizeof(u32);
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}
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mutex_unlock(&vpd->lock);
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return ret ? ret : count;
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}
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void pci_vpd_init(struct pci_dev *dev)
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{
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if (dev->vpd.len == PCI_VPD_SZ_INVALID)
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return;
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dev->vpd.cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
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mutex_init(&dev->vpd.lock);
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}
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static ssize_t vpd_read(struct file *filp, struct kobject *kobj,
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struct bin_attribute *bin_attr, char *buf, loff_t off,
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size_t count)
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{
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struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
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return pci_read_vpd(dev, off, count, buf);
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}
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static ssize_t vpd_write(struct file *filp, struct kobject *kobj,
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struct bin_attribute *bin_attr, char *buf, loff_t off,
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size_t count)
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{
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struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
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return pci_write_vpd(dev, off, count, buf);
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}
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static BIN_ATTR(vpd, 0600, vpd_read, vpd_write, 0);
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static struct bin_attribute *vpd_attrs[] = {
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&bin_attr_vpd,
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NULL,
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};
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static umode_t vpd_attr_is_visible(struct kobject *kobj,
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struct bin_attribute *a, int n)
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{
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struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
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if (!pdev->vpd.cap)
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return 0;
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return a->attr.mode;
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}
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const struct attribute_group pci_dev_vpd_attr_group = {
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.bin_attrs = vpd_attrs,
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.is_bin_visible = vpd_attr_is_visible,
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};
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void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size)
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{
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unsigned int len;
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void *buf;
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int cnt;
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if (!pci_vpd_available(dev, true))
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return ERR_PTR(-ENODEV);
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len = dev->vpd.len;
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buf = kmalloc(len, GFP_KERNEL);
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if (!buf)
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return ERR_PTR(-ENOMEM);
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cnt = pci_read_vpd(dev, 0, len, buf);
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if (cnt != len) {
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kfree(buf);
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return ERR_PTR(-EIO);
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}
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if (size)
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*size = len;
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return buf;
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}
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EXPORT_SYMBOL_GPL(pci_vpd_alloc);
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static int pci_vpd_find_tag(const u8 *buf, unsigned int len, u8 rdt, unsigned int *size)
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{
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int i = 0;
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/* look for LRDT tags only, end tag is the only SRDT tag */
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while (i + PCI_VPD_LRDT_TAG_SIZE <= len && buf[i] & PCI_VPD_LRDT) {
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unsigned int lrdt_len = pci_vpd_lrdt_size(buf + i);
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u8 tag = buf[i];
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i += PCI_VPD_LRDT_TAG_SIZE;
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if (tag == rdt) {
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if (i + lrdt_len > len)
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lrdt_len = len - i;
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if (size)
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*size = lrdt_len;
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return i;
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}
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i += lrdt_len;
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}
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return -ENOENT;
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}
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int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size)
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{
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return pci_vpd_find_tag(buf, len, PCI_VPD_LRDT_ID_STRING, size);
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}
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EXPORT_SYMBOL_GPL(pci_vpd_find_id_string);
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static int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
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unsigned int len, const char *kw)
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{
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int i;
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for (i = off; i + PCI_VPD_INFO_FLD_HDR_SIZE <= off + len;) {
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if (buf[i + 0] == kw[0] &&
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buf[i + 1] == kw[1])
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return i;
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i += PCI_VPD_INFO_FLD_HDR_SIZE +
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pci_vpd_info_field_size(&buf[i]);
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}
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return -ENOENT;
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}
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static ssize_t __pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf,
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bool check_size)
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{
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ssize_t ret;
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if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
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dev = pci_get_func0_dev(dev);
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if (!dev)
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return -ENODEV;
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ret = pci_vpd_read(dev, pos, count, buf, check_size);
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pci_dev_put(dev);
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return ret;
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}
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return pci_vpd_read(dev, pos, count, buf, check_size);
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}
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/**
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* pci_read_vpd - Read one entry from Vital Product Data
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* @dev: PCI device struct
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* @pos: offset in VPD space
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* @count: number of bytes to read
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* @buf: pointer to where to store result
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*/
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ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
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{
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return __pci_read_vpd(dev, pos, count, buf, true);
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}
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EXPORT_SYMBOL(pci_read_vpd);
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/* Same, but allow to access any address */
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ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
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{
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return __pci_read_vpd(dev, pos, count, buf, false);
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}
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EXPORT_SYMBOL(pci_read_vpd_any);
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static ssize_t __pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count,
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const void *buf, bool check_size)
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{
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ssize_t ret;
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if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
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dev = pci_get_func0_dev(dev);
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if (!dev)
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return -ENODEV;
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ret = pci_vpd_write(dev, pos, count, buf, check_size);
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pci_dev_put(dev);
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return ret;
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}
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return pci_vpd_write(dev, pos, count, buf, check_size);
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}
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/**
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* pci_write_vpd - Write entry to Vital Product Data
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* @dev: PCI device struct
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* @pos: offset in VPD space
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* @count: number of bytes to write
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* @buf: buffer containing write data
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*/
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ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
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{
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return __pci_write_vpd(dev, pos, count, buf, true);
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}
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EXPORT_SYMBOL(pci_write_vpd);
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/* Same, but allow to access any address */
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ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
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{
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return __pci_write_vpd(dev, pos, count, buf, false);
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}
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EXPORT_SYMBOL(pci_write_vpd_any);
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int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
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const char *kw, unsigned int *size)
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{
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int ro_start, infokw_start;
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unsigned int ro_len, infokw_size;
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ro_start = pci_vpd_find_tag(buf, len, PCI_VPD_LRDT_RO_DATA, &ro_len);
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if (ro_start < 0)
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return ro_start;
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infokw_start = pci_vpd_find_info_keyword(buf, ro_start, ro_len, kw);
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if (infokw_start < 0)
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return infokw_start;
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infokw_size = pci_vpd_info_field_size(buf + infokw_start);
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infokw_start += PCI_VPD_INFO_FLD_HDR_SIZE;
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if (infokw_start + infokw_size > len)
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return -EINVAL;
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if (size)
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*size = infokw_size;
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return infokw_start;
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}
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EXPORT_SYMBOL_GPL(pci_vpd_find_ro_info_keyword);
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int pci_vpd_check_csum(const void *buf, unsigned int len)
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{
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const u8 *vpd = buf;
|
|
unsigned int size;
|
|
u8 csum = 0;
|
|
int rv_start;
|
|
|
|
rv_start = pci_vpd_find_ro_info_keyword(buf, len, PCI_VPD_RO_KEYWORD_CHKSUM, &size);
|
|
if (rv_start == -ENOENT) /* no checksum in VPD */
|
|
return 1;
|
|
else if (rv_start < 0)
|
|
return rv_start;
|
|
|
|
if (!size)
|
|
return -EINVAL;
|
|
|
|
while (rv_start >= 0)
|
|
csum += vpd[rv_start--];
|
|
|
|
return csum ? -EILSEQ : 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_vpd_check_csum);
|
|
|
|
#ifdef CONFIG_PCI_QUIRKS
|
|
/*
|
|
* Quirk non-zero PCI functions to route VPD access through function 0 for
|
|
* devices that share VPD resources between functions. The functions are
|
|
* expected to be identical devices.
|
|
*/
|
|
static void quirk_f0_vpd_link(struct pci_dev *dev)
|
|
{
|
|
struct pci_dev *f0;
|
|
|
|
if (!PCI_FUNC(dev->devfn))
|
|
return;
|
|
|
|
f0 = pci_get_func0_dev(dev);
|
|
if (!f0)
|
|
return;
|
|
|
|
if (f0->vpd.cap && dev->class == f0->class &&
|
|
dev->vendor == f0->vendor && dev->device == f0->device)
|
|
dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
|
|
|
|
pci_dev_put(f0);
|
|
}
|
|
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
|
|
PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
|
|
|
|
/*
|
|
* If a device follows the VPD format spec, the PCI core will not read or
|
|
* write past the VPD End Tag. But some vendors do not follow the VPD
|
|
* format spec, so we can't tell how much data is safe to access. Devices
|
|
* may behave unpredictably if we access too much. Blacklist these devices
|
|
* so we don't touch VPD at all.
|
|
*/
|
|
static void quirk_blacklist_vpd(struct pci_dev *dev)
|
|
{
|
|
dev->vpd.len = PCI_VPD_SZ_INVALID;
|
|
pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID, quirk_blacklist_vpd);
|
|
/*
|
|
* The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
|
|
* device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
|
|
*/
|
|
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
|
|
PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);
|
|
|
|
static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
|
|
{
|
|
int chip = (dev->device & 0xf000) >> 12;
|
|
int func = (dev->device & 0x0f00) >> 8;
|
|
int prod = (dev->device & 0x00ff) >> 0;
|
|
|
|
/*
|
|
* If this is a T3-based adapter, there's a 1KB VPD area at offset
|
|
* 0xc00 which contains the preferred VPD values. If this is a T4 or
|
|
* later based adapter, the special VPD is at offset 0x400 for the
|
|
* Physical Functions (the SR-IOV Virtual Functions have no VPD
|
|
* Capabilities). The PCI VPD Access core routines will normally
|
|
* compute the size of the VPD by parsing the VPD Data Structure at
|
|
* offset 0x000. This will result in silent failures when attempting
|
|
* to accesses these other VPD areas which are beyond those computed
|
|
* limits.
|
|
*/
|
|
if (chip == 0x0 && prod >= 0x20)
|
|
dev->vpd.len = 8192;
|
|
else if (chip >= 0x4 && func < 0x8)
|
|
dev->vpd.len = 2048;
|
|
}
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
|
|
quirk_chelsio_extend_vpd);
|
|
|
|
#endif
|