mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 13:55:32 +00:00
4a33bea003
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
13 lines
304 B
Text
13 lines
304 B
Text
# SPDX-License-Identifier: GPL-2.0-only
|
|
|
|
#
|
|
# PHY drivers for Xilinx platforms
|
|
#
|
|
|
|
config PHY_XILINX_ZYNQMP
|
|
tristate "Xilinx ZynqMP PHY driver"
|
|
depends on ARCH_ZYNQMP || COMPILE_TEST
|
|
select GENERIC_PHY
|
|
help
|
|
Enable this to support ZynqMP High Speed Gigabit Transceiver
|
|
that is part of ZynqMP SoC.
|