linux-stable/drivers/pinctrl/qcom
Douglas Anderson 80dcb581c4 pinctrl: qcom: Avoid glitching lines when we first mux to output
[ Upstream commit d21f4b7ffc ]

Back in the description of commit e440e30e26 ("arm64: dts: qcom:
sc7180: Avoid glitching SPI CS at bootup on trogdor") we described a
problem that we were seeing on trogdor devices. I'll re-summarize here
but you can also re-read the original commit.

On trogdor devices, the BIOS is setting up the SPI chip select as:
- mux special function (SPI chip select)
- output enable
- output low (unused because we've muxed as special function)

In the kernel, however, we've moved away from using the chip select
line as special function. Since the kernel wants to fully control the
chip select it's far more efficient to treat the line as a GPIO rather
than sending packet-like commands to the GENI firmware every time we
want the line to toggle.

When we transition from how the BIOS had the pin configured to how the
kernel has the pin configured we end up glitching the line. That's
because we _first_ change the mux of the line and then later set its
output. This glitch is bad and can confuse the device on the other end
of the line.

The old commit e440e30e26 ("arm64: dts: qcom: sc7180: Avoid
glitching SPI CS at bootup on trogdor") fixed the glitch, though the
solution was far from elegant. It essentially did the thing that
everyone always hates: encoding a sequential program in device tree,
even if it's a simple one. It also, unfortunately, got broken by
commit b991f8c362 ("pinctrl: core: Handling pinmux and pinconf
separately"). After that commit we did all the muxing _first_ even
though the config (set the pin to output high) was listed first. :(

I looked at ideas for how to solve this more properly. My first
thought was to use the "init" pinctrl state. In theory the "init"
pinctrl state is supposed to be exactly for achieving glitch-free
transitions. My dream would have been for the "init" pinctrl to do
nothing at all. That would let us delay the automatic pin muxing until
the driver could set things up and call pinctrl_init_done(). In other
words, my dream was:

  /* Request the GPIO; init it 1 (because DT says GPIO_ACTIVE_LOW) */
  devm_gpiod_get_index(dev, "cs", GPIOD_OUT_LOW);
  /* Output should be right, so we can remux, yay! */
  pinctrl_init_done(dev);

Unfortunately, it didn't work out. The primary reason is that the MSM
GPIO driver implements gpio_request_enable(). As documented in
pinmux.h, that function automatically remuxes a line as a GPIO. ...and
it does this remuxing _before_ specifying the output of the pin. You
can see in gpiod_get_index() that we call gpiod_request() before
gpiod_configure_flags(). gpiod_request() isn't passed any flags so it
has no idea what the eventual output will be.

We could have debates about whether or not the automatic remuxing to
GPIO for the MSM pinctrl was a good idea or not, but at this point I
think there is a plethora of code that's relying on it and I certainly
wouldn't suggest changing it.

Alternatively, we could try to come up with a way to pass the initial
output state to gpio_request_enable() and plumb all that through. That
seems like it would be doable, but we'd have to plumb it through
several layers in the stack.

This patch implements yet another alternative. Here, we specifically
avoid glitching the first time a pin is muxed to GPIO function if the
direction of the pin is output. The idea is that we can read the state
of the pin before we set the mux and make sure that the re-mux won't
change the state.

NOTES:
- We only do this the first time since later swaps between mux states
  might want to preserve the old output value. In other words, I
  wouldn't want to break a driver that did:
     gpiod_set_value(g, 1);
     pinctrl_select_state(pinctrl, special_state);
     pinctrl_select_default_state();
     /* We should be driving 1 even if "special_state" made the pin 0 */
- It's safe to do this the first time since the driver _couldn't_ have
  explicitly set a state. In order to even be able to control the GPIO
  (at least using gpiod) we have to have requested it which would have
  counted as the first mux.
- In theory, instead of keeping track of the first time a pin was set
  as a GPIO we could enable the glitch-free behavior only when
  msm_pinmux_request_gpio() is in the callchain. That works an enables
  my "dream" implementation above where we use an "init" state to
  solve this. However, it's nice not to have to do this. By handling
  just the first transition to GPIO we can simply let the normal
  "default" remuxing happen and we can be assured that there won't be
  a glitch.

Before this change I could see the glitch reported on the EC console
when booting. It would say this when booting the kernel:
  Unexpected state 1 in CSNRE ISR

After this change there is no error reported.

Note that I haven't reproduced the original problem described in
e440e30e26 ("arm64: dts: qcom: sc7180: Avoid glitching SPI CS at
bootup on trogdor") but I could believe it might happen in certain
timing conditions.

Fixes: b991f8c362 ("pinctrl: core: Handling pinmux and pinconf separately")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20221014103217.1.I656bb2c976ed626e5d37294eb252c1cf3be769dc@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-11-04 00:00:27 +09:00
..
Kconfig pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM 2022-08-03 20:31:14 +02:00
Makefile pinctrl: qcom: Add SM6375 TLMM driver 2022-07-26 09:28:53 +02:00
pinctrl-apq8064.c
pinctrl-apq8084.c
pinctrl-ipq4019.c pinctrl: qcom: ipq4019: add open drain support 2020-07-16 10:46:24 +02:00
pinctrl-ipq6018.c pinctrl: qcom: ipq6018 Add missing pins in qpic pin group 2020-06-20 22:05:24 +02:00
pinctrl-ipq8064.c
pinctrl-ipq8074.c pinctrl: qcom: ipq8074: route gpio interrupts to APPS 2020-07-11 23:11:00 +02:00
pinctrl-lpass-lpi.c pinctrl: qcom: sc7280: Fix compile bug 2022-06-30 14:00:53 +02:00
pinctrl-lpass-lpi.h pinctrl: qcom: sc7280: Fix compile bug 2022-06-30 14:00:53 +02:00
pinctrl-mdm9607.c pinctrl: qcom: Add MDM9607 pinctrl driver 2021-07-23 17:44:13 +02:00
pinctrl-mdm9615.c
pinctrl-msm.c pinctrl: qcom: Avoid glitching lines when we first mux to output 2022-11-04 00:00:27 +09:00
pinctrl-msm.h pinctrl: qcom: Add egpio feature support 2021-11-22 00:27:54 +01:00
pinctrl-msm8x74.c
pinctrl-msm8226.c pinctrl: qcom: msm8226: fill in more functions 2021-09-18 00:31:10 +02:00
pinctrl-msm8660.c
pinctrl-msm8909.c pinctrl: qcom: Add pinctrl driver for MSM8909 2022-07-11 10:26:52 +02:00
pinctrl-msm8916.c pinctrl: qcom: msm8916: Allow CAMSS GP clocks to be muxed 2022-06-26 00:54:10 +02:00
pinctrl-msm8953.c pinctrl: qcom: add pinctrl driver for msm8953 2020-11-10 14:58:14 +01:00
pinctrl-msm8960.c
pinctrl-msm8976.c pinctrl: qcom: pinctrl-msm8976: Remove unused variable 'nav_tsync_groups' 2020-07-16 15:12:38 +02:00
pinctrl-msm8994.c
pinctrl-msm8996.c
pinctrl-msm8998.c
pinctrl-qcm2290.c pinctrl: qcom: qcm2290: Add GPIO wakeirq map 2022-02-19 01:59:19 +01:00
pinctrl-qcs404.c
pinctrl-qdf2xxx.c
pinctrl-sc7180.c pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180 2020-07-16 15:41:41 +02:00
pinctrl-sc7280-lpass-lpi.c pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets 2022-06-26 00:50:41 +02:00
pinctrl-sc7280.c pinctrl: qcom: sc7280: Add egpio support 2021-11-22 00:27:54 +01:00
pinctrl-sc8180x.c pinctrl: qcom: sc8180x: Fix wrong pin numbers 2022-08-22 10:57:07 +02:00
pinctrl-sc8280xp.c pinctrl: qcom: Introduce sc8280xp TLMM driver 2022-03-15 02:03:46 +01:00
pinctrl-sdm660.c
pinctrl-sdm845.c pinctrl: qcom: sdm845: Enable dual edge errata 2021-11-16 02:19:15 +01:00
pinctrl-sdx55.c pinctrl: qcom: Fix duplication in gpio_groups 2021-06-07 00:18:55 +02:00
pinctrl-sdx65.c pinctrl: qcom: Add SDX65 pincontrol driver 2021-11-21 23:48:27 +01:00
pinctrl-sm6115.c drivers: qcom: pinctrl: Add pinctrl driver for sm6115 2021-07-31 23:23:06 +02:00
pinctrl-sm6125.c pinctrl: qcom: cleanup comments 2022-03-15 01:30:37 +01:00
pinctrl-sm6350.c pinctrl: qcom: sm6350: fix order of UFS & SDC pins 2022-04-18 01:38:24 +02:00
pinctrl-sm6375.c pinctrl: qcom: Add SM6375 TLMM driver 2022-07-26 09:28:53 +02:00
pinctrl-sm8150.c pinctrl: qcom: sm8150: Specify PDC map 2022-04-18 01:09:42 +02:00
pinctrl-sm8250-lpass-lpi.c pinctrl: qcom: Extract chip specific LPASS LPI code 2022-04-23 00:04:43 +02:00
pinctrl-sm8250.c pinctrl: qcom: sm8250: Fix PDC map 2022-08-03 20:20:56 +02:00
pinctrl-sm8350.c pinctrl: qcom: sm8350: Correct UFS and SDC offsets 2021-11-16 02:19:15 +01:00
pinctrl-sm8450.c pinctrl: qcom: sm8450: Add egpio support 2022-02-19 01:53:55 +01:00
pinctrl-spmi-gpio.c Pin control bulk changes for v6.0: 2022-08-10 11:01:44 -07:00
pinctrl-spmi-mpp.c pinctrl: qcom: spmi-mpp: Add PM8226 compatible 2022-02-11 01:08:06 +01:00
pinctrl-ssbi-gpio.c pinctrl: Get rid of duplicate of_node assignment in the drivers 2021-12-16 04:18:30 +01:00
pinctrl-ssbi-mpp.c pinctrl: Get rid of duplicate of_node assignment in the drivers 2021-12-16 04:18:30 +01:00