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![Srinivas Kandagatla](/assets/img/avatar_default.png)
[ Upstream commit49a467310d
] Reading will increase the fifo count, so check for outstanding cmd wrt. write fifo depth to avoid overflow as read will also increase write fifo cnt. Fixes:a661308c34
("soundwire: qcom: wait for fifo space to be available before read/write") Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20221026110210.6575-3-srinivas.kandagatla@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
1604 lines
44 KiB
C
1604 lines
44 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2019, Linaro Limited
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/debugfs.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/slimbus.h>
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#include <linux/soundwire/sdw.h>
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#include <linux/soundwire/sdw_registers.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "bus.h"
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#define SWRM_COMP_SW_RESET 0x008
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#define SWRM_COMP_STATUS 0x014
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#define SWRM_FRM_GEN_ENABLED BIT(0)
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#define SWRM_COMP_HW_VERSION 0x00
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#define SWRM_COMP_CFG_ADDR 0x04
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#define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
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#define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
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#define SWRM_COMP_PARAMS 0x100
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#define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10)
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#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)
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#define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
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#define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
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#define SWRM_COMP_MASTER_ID 0x104
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#define SWRM_INTERRUPT_STATUS 0x200
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#define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
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#define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
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#define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
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#define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
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#define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3)
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#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4)
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#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5)
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#define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6)
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#define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
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#define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8)
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#define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9)
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#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
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#define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13)
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#define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14)
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#define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16)
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#define SWRM_INTERRUPT_MAX 17
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#define SWRM_INTERRUPT_MASK_ADDR 0x204
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#define SWRM_INTERRUPT_CLEAR 0x208
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#define SWRM_INTERRUPT_CPU_EN 0x210
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#define SWRM_CMD_FIFO_WR_CMD 0x300
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#define SWRM_CMD_FIFO_RD_CMD 0x304
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#define SWRM_CMD_FIFO_CMD 0x308
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#define SWRM_CMD_FIFO_FLUSH 0x1
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#define SWRM_CMD_FIFO_STATUS 0x30C
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#define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16)
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#define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8)
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#define SWRM_CMD_FIFO_CFG_ADDR 0x314
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#define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31)
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#define SWRM_RD_WR_CMD_RETRIES 0x7
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#define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318
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#define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)
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#define SWRM_ENUMERATOR_CFG_ADDR 0x500
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#define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
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#define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m))
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#define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
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#define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
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#define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
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#define SWRM_MCP_BUS_CTRL 0x1044
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#define SWRM_MCP_BUS_CLK_START BIT(1)
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#define SWRM_MCP_CFG_ADDR 0x1048
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#define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
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#define SWRM_DEF_CMD_NO_PINGS 0x1f
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#define SWRM_MCP_STATUS 0x104C
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#define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
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#define SWRM_MCP_SLV_STATUS 0x1090
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#define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
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#define SWRM_MCP_SLV_STATUS_SZ 2
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#define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
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#define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
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#define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
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#define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
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#define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
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#define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
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#define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
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#define SWR_MSTR_MAX_REG_ADDR (0x1740)
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#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
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#define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
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#define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
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#define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
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#define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
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#define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
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#define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
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#define SWRM_REG_VAL_PACK(data, dev, id, reg) \
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((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
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#define SWRM_SPECIAL_CMD_ID 0xF
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#define MAX_FREQ_NUM 1
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#define TIMEOUT_MS 100
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#define QCOM_SWRM_MAX_RD_LEN 0x1
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#define QCOM_SDW_MAX_PORTS 14
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#define DEFAULT_CLK_FREQ 9600000
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#define SWRM_MAX_DAIS 0xF
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#define SWR_INVALID_PARAM 0xFF
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#define SWR_HSTOP_MAX_VAL 0xF
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#define SWR_HSTART_MIN_VAL 0x0
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#define SWR_BROADCAST_CMD_ID 0x0F
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#define SWR_MAX_CMD_ID 14
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#define MAX_FIFO_RD_RETRY 3
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#define SWR_OVERFLOW_RETRY_COUNT 30
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#define SWRM_LINK_STATUS_RETRY_CNT 100
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enum {
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MASTER_ID_WSA = 1,
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MASTER_ID_RX,
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MASTER_ID_TX
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};
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struct qcom_swrm_port_config {
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u8 si;
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u8 off1;
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u8 off2;
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u8 bp_mode;
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u8 hstart;
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u8 hstop;
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u8 word_length;
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u8 blk_group_count;
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u8 lane_control;
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};
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struct qcom_swrm_ctrl {
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struct sdw_bus bus;
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struct device *dev;
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struct regmap *regmap;
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void __iomem *mmio;
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struct reset_control *audio_cgcr;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs;
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#endif
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struct completion broadcast;
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struct completion enumeration;
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struct work_struct slave_work;
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/* Port alloc/free lock */
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struct mutex port_lock;
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struct clk *hclk;
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u8 wr_cmd_id;
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u8 rd_cmd_id;
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int irq;
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unsigned int version;
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int wake_irq;
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int num_din_ports;
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int num_dout_ports;
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int cols_index;
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int rows_index;
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unsigned long dout_port_mask;
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unsigned long din_port_mask;
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u32 intr_mask;
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u8 rcmd_id;
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u8 wcmd_id;
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struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
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struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
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enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
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int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
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int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
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u32 slave_status;
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u32 wr_fifo_depth;
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u32 rd_fifo_depth;
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bool clock_stop_not_supported;
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};
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struct qcom_swrm_data {
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u32 default_cols;
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u32 default_rows;
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bool sw_clk_gate_required;
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};
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static const struct qcom_swrm_data swrm_v1_3_data = {
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.default_rows = 48,
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.default_cols = 16,
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};
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static const struct qcom_swrm_data swrm_v1_5_data = {
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.default_rows = 50,
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.default_cols = 16,
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};
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static const struct qcom_swrm_data swrm_v1_6_data = {
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.default_rows = 50,
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.default_cols = 16,
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.sw_clk_gate_required = true,
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};
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#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
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static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
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u32 *val)
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{
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struct regmap *wcd_regmap = ctrl->regmap;
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int ret;
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/* pg register + offset */
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ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
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(u8 *)®, 4);
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if (ret < 0)
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return SDW_CMD_FAIL;
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ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
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val, 4);
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if (ret < 0)
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return SDW_CMD_FAIL;
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return SDW_CMD_OK;
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}
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static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
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int reg, int val)
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{
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struct regmap *wcd_regmap = ctrl->regmap;
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int ret;
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/* pg register + offset */
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ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
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(u8 *)&val, 4);
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if (ret)
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return SDW_CMD_FAIL;
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/* write address register */
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ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
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(u8 *)®, 4);
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if (ret)
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return SDW_CMD_FAIL;
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return SDW_CMD_OK;
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}
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static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
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u32 *val)
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{
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*val = readl(ctrl->mmio + reg);
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return SDW_CMD_OK;
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}
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static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
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int val)
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{
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writel(val, ctrl->mmio + reg);
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return SDW_CMD_OK;
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}
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static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
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u8 dev_addr, u16 reg_addr)
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{
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u32 val;
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u8 id = *cmd_id;
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if (id != SWR_BROADCAST_CMD_ID) {
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if (id < SWR_MAX_CMD_ID)
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id += 1;
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else
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id = 0;
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*cmd_id = id;
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}
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val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
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return val;
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}
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static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
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{
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u32 fifo_outstanding_data, value;
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int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
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do {
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/* Check for fifo underflow during read */
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swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
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fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
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/* Check if read data is available in read fifo */
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if (fifo_outstanding_data > 0)
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return 0;
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usleep_range(500, 510);
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} while (fifo_retry_count--);
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if (fifo_outstanding_data == 0) {
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dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
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return -EIO;
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}
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return 0;
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}
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static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
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{
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u32 fifo_outstanding_cmds, value;
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int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
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do {
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/* Check for fifo overflow during write */
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swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
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fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
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/* Check for space in write fifo before writing */
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if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
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return 0;
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usleep_range(500, 510);
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} while (fifo_retry_count--);
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if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
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dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
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return -EIO;
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}
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return 0;
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}
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static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
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u8 dev_addr, u16 reg_addr)
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{
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u32 val;
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int ret = 0;
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u8 cmd_id = 0x0;
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if (dev_addr == SDW_BROADCAST_DEV_NUM) {
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cmd_id = SWR_BROADCAST_CMD_ID;
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val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
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dev_addr, reg_addr);
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} else {
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val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
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dev_addr, reg_addr);
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}
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if (swrm_wait_for_wr_fifo_avail(swrm))
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return SDW_CMD_FAIL_OTHER;
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if (cmd_id == SWR_BROADCAST_CMD_ID)
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reinit_completion(&swrm->broadcast);
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/* Its assumed that write is okay as we do not get any status back */
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swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
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/* version 1.3 or less */
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if (swrm->version <= 0x01030000)
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usleep_range(150, 155);
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if (cmd_id == SWR_BROADCAST_CMD_ID) {
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/*
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* sleep for 10ms for MSM soundwire variant to allow broadcast
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* command to complete.
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*/
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ret = wait_for_completion_timeout(&swrm->broadcast,
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msecs_to_jiffies(TIMEOUT_MS));
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if (!ret)
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ret = SDW_CMD_IGNORED;
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else
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ret = SDW_CMD_OK;
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} else {
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ret = SDW_CMD_OK;
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}
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return ret;
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}
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static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
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u8 dev_addr, u16 reg_addr,
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u32 len, u8 *rval)
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{
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u32 cmd_data, cmd_id, val, retry_attempt = 0;
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val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
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/*
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* Check for outstanding cmd wrt. write fifo depth to avoid
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* overflow as read will also increase write fifo cnt.
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*/
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swrm_wait_for_wr_fifo_avail(swrm);
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/* wait for FIFO RD to complete to avoid overflow */
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usleep_range(100, 105);
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swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
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/* wait for FIFO RD CMD complete to avoid overflow */
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usleep_range(250, 255);
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if (swrm_wait_for_rd_fifo_avail(swrm))
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return SDW_CMD_FAIL_OTHER;
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do {
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swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
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rval[0] = cmd_data & 0xFF;
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cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
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if (cmd_id != swrm->rcmd_id) {
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if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
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/* wait 500 us before retry on fifo read failure */
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usleep_range(500, 505);
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swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
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SWRM_CMD_FIFO_FLUSH);
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swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
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}
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retry_attempt++;
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} else {
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return SDW_CMD_OK;
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}
|
|
|
|
} while (retry_attempt < MAX_FIFO_RD_RETRY);
|
|
|
|
dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
|
|
dev_num: 0x%x, cmd_data: 0x%x\n",
|
|
reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
|
|
|
|
return SDW_CMD_IGNORED;
|
|
}
|
|
|
|
static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
|
|
{
|
|
u32 val, status;
|
|
int dev_num;
|
|
|
|
ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
|
|
|
|
for (dev_num = 0; dev_num <= SDW_MAX_DEVICES; dev_num++) {
|
|
status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
|
|
|
|
if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
|
|
ctrl->status[dev_num] = status;
|
|
return dev_num;
|
|
}
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
|
|
{
|
|
u32 val;
|
|
int i;
|
|
|
|
ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
|
|
ctrl->slave_status = val;
|
|
|
|
for (i = 0; i <= SDW_MAX_DEVICES; i++) {
|
|
u32 s;
|
|
|
|
s = (val >> (i * 2));
|
|
s &= SWRM_MCP_SLV_STATUS_MASK;
|
|
ctrl->status[i] = s;
|
|
}
|
|
}
|
|
|
|
static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
|
|
struct sdw_slave *slave, int devnum)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
|
u32 status;
|
|
|
|
ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
|
|
status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
|
|
status &= SWRM_MCP_SLV_STATUS_MASK;
|
|
|
|
if (status == SDW_SLAVE_ATTACHED) {
|
|
if (slave)
|
|
slave->dev_num = devnum;
|
|
mutex_lock(&bus->bus_lock);
|
|
set_bit(devnum, bus->assigned);
|
|
mutex_unlock(&bus->bus_lock);
|
|
}
|
|
}
|
|
|
|
static int qcom_swrm_enumerate(struct sdw_bus *bus)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
|
struct sdw_slave *slave, *_s;
|
|
struct sdw_slave_id id;
|
|
u32 val1, val2;
|
|
bool found;
|
|
u64 addr;
|
|
int i;
|
|
char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
|
|
|
|
for (i = 1; i <= SDW_MAX_DEVICES; i++) {
|
|
/* do not continue if the status is Not Present */
|
|
if (!ctrl->status[i])
|
|
continue;
|
|
|
|
/*SCP_Devid5 - Devid 4*/
|
|
ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
|
|
|
|
/*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
|
|
ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
|
|
|
|
if (!val1 && !val2)
|
|
break;
|
|
|
|
addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
|
|
((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
|
|
((u64)buf1[0] << 40);
|
|
|
|
sdw_extract_slave_id(bus, addr, &id);
|
|
found = false;
|
|
/* Now compare with entries */
|
|
list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
|
|
if (sdw_compare_devid(slave, id) == 0) {
|
|
qcom_swrm_set_slave_dev_num(bus, slave, i);
|
|
found = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!found) {
|
|
qcom_swrm_set_slave_dev_num(bus, NULL, i);
|
|
sdw_slave_add(bus, &id, NULL);
|
|
}
|
|
}
|
|
|
|
complete(&ctrl->enumeration);
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
|
|
{
|
|
struct qcom_swrm_ctrl *swrm = dev_id;
|
|
int ret;
|
|
|
|
ret = pm_runtime_resume_and_get(swrm->dev);
|
|
if (ret < 0 && ret != -EACCES) {
|
|
dev_err_ratelimited(swrm->dev,
|
|
"pm_runtime_resume_and_get failed in %s, ret %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
if (swrm->wake_irq > 0) {
|
|
if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq)))
|
|
disable_irq_nosync(swrm->wake_irq);
|
|
}
|
|
|
|
pm_runtime_mark_last_busy(swrm->dev);
|
|
pm_runtime_put_autosuspend(swrm->dev);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
|
|
{
|
|
struct qcom_swrm_ctrl *swrm = dev_id;
|
|
u32 value, intr_sts, intr_sts_masked, slave_status;
|
|
u32 i;
|
|
int devnum;
|
|
int ret = IRQ_HANDLED;
|
|
clk_prepare_enable(swrm->hclk);
|
|
|
|
swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
|
|
intr_sts_masked = intr_sts & swrm->intr_mask;
|
|
|
|
do {
|
|
for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
|
|
value = intr_sts_masked & BIT(i);
|
|
if (!value)
|
|
continue;
|
|
|
|
switch (value) {
|
|
case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
|
|
devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
|
|
if (devnum < 0) {
|
|
dev_err_ratelimited(swrm->dev,
|
|
"no slave alert found.spurious interrupt\n");
|
|
} else {
|
|
sdw_handle_slave_status(&swrm->bus, swrm->status);
|
|
}
|
|
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
|
|
case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
|
|
dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n",
|
|
__func__);
|
|
swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
|
|
if (swrm->slave_status == slave_status) {
|
|
dev_err(swrm->dev, "Slave status not changed %x\n",
|
|
slave_status);
|
|
} else {
|
|
qcom_swrm_get_device_status(swrm);
|
|
qcom_swrm_enumerate(&swrm->bus);
|
|
sdw_handle_slave_status(&swrm->bus, swrm->status);
|
|
}
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
|
|
dev_err_ratelimited(swrm->dev,
|
|
"%s: SWR bus clsh detected\n",
|
|
__func__);
|
|
swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
|
|
swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
|
|
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
|
|
dev_err_ratelimited(swrm->dev,
|
|
"%s: SWR read FIFO overflow fifo status 0x%x\n",
|
|
__func__, value);
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
|
|
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
|
|
dev_err_ratelimited(swrm->dev,
|
|
"%s: SWR read FIFO underflow fifo status 0x%x\n",
|
|
__func__, value);
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
|
|
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
|
|
dev_err(swrm->dev,
|
|
"%s: SWR write FIFO overflow fifo status %x\n",
|
|
__func__, value);
|
|
swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_CMD_ERROR:
|
|
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
|
|
dev_err_ratelimited(swrm->dev,
|
|
"%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
|
|
__func__, value);
|
|
swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
|
|
dev_err_ratelimited(swrm->dev,
|
|
"%s: SWR Port collision detected\n",
|
|
__func__);
|
|
swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
|
|
swrm->reg_write(swrm,
|
|
SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
|
|
dev_err_ratelimited(swrm->dev,
|
|
"%s: SWR read enable valid mismatch\n",
|
|
__func__);
|
|
swrm->intr_mask &=
|
|
~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
|
|
swrm->reg_write(swrm,
|
|
SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
|
|
complete(&swrm->broadcast);
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
|
|
break;
|
|
case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
|
|
break;
|
|
default:
|
|
dev_err_ratelimited(swrm->dev,
|
|
"%s: SWR unknown interrupt value: %d\n",
|
|
__func__, value);
|
|
ret = IRQ_NONE;
|
|
break;
|
|
}
|
|
}
|
|
swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
|
|
swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
|
|
intr_sts_masked = intr_sts & swrm->intr_mask;
|
|
} while (intr_sts_masked);
|
|
|
|
clk_disable_unprepare(swrm->hclk);
|
|
return ret;
|
|
}
|
|
|
|
static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
|
|
{
|
|
u32 val;
|
|
|
|
/* Clear Rows and Cols */
|
|
val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
|
|
val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
|
|
|
|
reset_control_reset(ctrl->audio_cgcr);
|
|
|
|
ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
|
|
|
|
/* Enable Auto enumeration */
|
|
ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
|
|
|
|
ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
|
|
/* Mask soundwire interrupts */
|
|
ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
|
|
SWRM_INTERRUPT_STATUS_RMSK);
|
|
|
|
/* Configure No pings */
|
|
ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
|
|
u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
|
|
ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
|
|
|
|
ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
|
|
/* Configure number of retries of a read/write cmd */
|
|
if (ctrl->version > 0x01050001) {
|
|
/* Only for versions >= 1.5.1 */
|
|
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
|
|
SWRM_RD_WR_CMD_RETRIES |
|
|
SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
|
|
} else {
|
|
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
|
|
SWRM_RD_WR_CMD_RETRIES);
|
|
}
|
|
|
|
/* Set IRQ to PULSE */
|
|
ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
|
|
SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
|
|
SWRM_COMP_CFG_ENABLE_MSK);
|
|
|
|
/* enable CPU IRQs */
|
|
if (ctrl->mmio) {
|
|
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
|
|
SWRM_INTERRUPT_STATUS_RMSK);
|
|
}
|
|
ctrl->slave_status = 0;
|
|
ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
|
|
ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
|
|
ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
|
|
struct sdw_msg *msg)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
|
int ret, i, len;
|
|
|
|
if (msg->flags == SDW_MSG_FLAG_READ) {
|
|
for (i = 0; i < msg->len;) {
|
|
if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
|
|
len = msg->len - i;
|
|
else
|
|
len = QCOM_SWRM_MAX_RD_LEN;
|
|
|
|
ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
|
|
msg->addr + i, len,
|
|
&msg->buf[i]);
|
|
if (ret)
|
|
return ret;
|
|
|
|
i = i + len;
|
|
}
|
|
} else if (msg->flags == SDW_MSG_FLAG_WRITE) {
|
|
for (i = 0; i < msg->len; i++) {
|
|
ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
|
|
msg->dev_num,
|
|
msg->addr + i);
|
|
if (ret)
|
|
return SDW_CMD_IGNORED;
|
|
}
|
|
}
|
|
|
|
return SDW_CMD_OK;
|
|
}
|
|
|
|
static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
|
|
{
|
|
u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
|
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
|
u32 val;
|
|
|
|
ctrl->reg_read(ctrl, reg, &val);
|
|
|
|
u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
|
|
u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
|
|
|
|
return ctrl->reg_write(ctrl, reg, val);
|
|
}
|
|
|
|
static int qcom_swrm_port_params(struct sdw_bus *bus,
|
|
struct sdw_port_params *p_params,
|
|
unsigned int bank)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
|
|
|
return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
|
|
p_params->bps - 1);
|
|
|
|
}
|
|
|
|
static int qcom_swrm_transport_params(struct sdw_bus *bus,
|
|
struct sdw_transport_params *params,
|
|
enum sdw_reg_bank bank)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
|
struct qcom_swrm_port_config *pcfg;
|
|
u32 value;
|
|
int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
|
|
int ret;
|
|
|
|
pcfg = &ctrl->pconfig[params->port_num];
|
|
|
|
value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
|
|
value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
|
|
value |= pcfg->si;
|
|
|
|
ret = ctrl->reg_write(ctrl, reg, value);
|
|
if (ret)
|
|
goto err;
|
|
|
|
if (pcfg->lane_control != SWR_INVALID_PARAM) {
|
|
reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
|
|
value = pcfg->lane_control;
|
|
ret = ctrl->reg_write(ctrl, reg, value);
|
|
if (ret)
|
|
goto err;
|
|
}
|
|
|
|
if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
|
|
reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
|
|
value = pcfg->blk_group_count;
|
|
ret = ctrl->reg_write(ctrl, reg, value);
|
|
if (ret)
|
|
goto err;
|
|
}
|
|
|
|
if (pcfg->hstart != SWR_INVALID_PARAM
|
|
&& pcfg->hstop != SWR_INVALID_PARAM) {
|
|
reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
|
|
value = (pcfg->hstop << 4) | pcfg->hstart;
|
|
ret = ctrl->reg_write(ctrl, reg, value);
|
|
} else {
|
|
reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
|
|
value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
|
|
ret = ctrl->reg_write(ctrl, reg, value);
|
|
}
|
|
|
|
if (ret)
|
|
goto err;
|
|
|
|
if (pcfg->bp_mode != SWR_INVALID_PARAM) {
|
|
reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
|
|
ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
|
|
}
|
|
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static int qcom_swrm_port_enable(struct sdw_bus *bus,
|
|
struct sdw_enable_ch *enable_ch,
|
|
unsigned int bank)
|
|
{
|
|
u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
|
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
|
u32 val;
|
|
|
|
ctrl->reg_read(ctrl, reg, &val);
|
|
|
|
if (enable_ch->enable)
|
|
val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
|
|
else
|
|
val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
|
|
|
|
return ctrl->reg_write(ctrl, reg, val);
|
|
}
|
|
|
|
static const struct sdw_master_port_ops qcom_swrm_port_ops = {
|
|
.dpn_set_port_params = qcom_swrm_port_params,
|
|
.dpn_set_port_transport_params = qcom_swrm_transport_params,
|
|
.dpn_port_enable_ch = qcom_swrm_port_enable,
|
|
};
|
|
|
|
static const struct sdw_master_ops qcom_swrm_ops = {
|
|
.xfer_msg = qcom_swrm_xfer_msg,
|
|
.pre_bank_switch = qcom_swrm_pre_bank_switch,
|
|
};
|
|
|
|
static int qcom_swrm_compute_params(struct sdw_bus *bus)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
|
struct sdw_master_runtime *m_rt;
|
|
struct sdw_slave_runtime *s_rt;
|
|
struct sdw_port_runtime *p_rt;
|
|
struct qcom_swrm_port_config *pcfg;
|
|
struct sdw_slave *slave;
|
|
unsigned int m_port;
|
|
int i = 1;
|
|
|
|
list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
|
|
list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
|
|
pcfg = &ctrl->pconfig[p_rt->num];
|
|
p_rt->transport_params.port_num = p_rt->num;
|
|
if (pcfg->word_length != SWR_INVALID_PARAM) {
|
|
sdw_fill_port_params(&p_rt->port_params,
|
|
p_rt->num, pcfg->word_length + 1,
|
|
SDW_PORT_FLOW_MODE_ISOCH,
|
|
SDW_PORT_DATA_MODE_NORMAL);
|
|
}
|
|
|
|
}
|
|
|
|
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
|
|
slave = s_rt->slave;
|
|
list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
|
|
m_port = slave->m_port_map[p_rt->num];
|
|
/* port config starts at offset 0 so -1 from actual port number */
|
|
if (m_port)
|
|
pcfg = &ctrl->pconfig[m_port];
|
|
else
|
|
pcfg = &ctrl->pconfig[i];
|
|
p_rt->transport_params.port_num = p_rt->num;
|
|
p_rt->transport_params.sample_interval =
|
|
pcfg->si + 1;
|
|
p_rt->transport_params.offset1 = pcfg->off1;
|
|
p_rt->transport_params.offset2 = pcfg->off2;
|
|
p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
|
|
p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
|
|
|
|
p_rt->transport_params.hstart = pcfg->hstart;
|
|
p_rt->transport_params.hstop = pcfg->hstop;
|
|
p_rt->transport_params.lane_ctrl = pcfg->lane_control;
|
|
if (pcfg->word_length != SWR_INVALID_PARAM) {
|
|
sdw_fill_port_params(&p_rt->port_params,
|
|
p_rt->num,
|
|
pcfg->word_length + 1,
|
|
SDW_PORT_FLOW_MODE_ISOCH,
|
|
SDW_PORT_DATA_MODE_NORMAL);
|
|
}
|
|
i++;
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
|
|
DEFAULT_CLK_FREQ,
|
|
};
|
|
|
|
static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
|
|
struct sdw_stream_runtime *stream)
|
|
{
|
|
struct sdw_master_runtime *m_rt;
|
|
struct sdw_port_runtime *p_rt;
|
|
unsigned long *port_mask;
|
|
|
|
mutex_lock(&ctrl->port_lock);
|
|
|
|
list_for_each_entry(m_rt, &stream->master_list, stream_node) {
|
|
if (m_rt->direction == SDW_DATA_DIR_RX)
|
|
port_mask = &ctrl->dout_port_mask;
|
|
else
|
|
port_mask = &ctrl->din_port_mask;
|
|
|
|
list_for_each_entry(p_rt, &m_rt->port_list, port_node)
|
|
clear_bit(p_rt->num, port_mask);
|
|
}
|
|
|
|
mutex_unlock(&ctrl->port_lock);
|
|
}
|
|
|
|
static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
|
|
struct sdw_stream_runtime *stream,
|
|
struct snd_pcm_hw_params *params,
|
|
int direction)
|
|
{
|
|
struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
|
|
struct sdw_stream_config sconfig;
|
|
struct sdw_master_runtime *m_rt;
|
|
struct sdw_slave_runtime *s_rt;
|
|
struct sdw_port_runtime *p_rt;
|
|
struct sdw_slave *slave;
|
|
unsigned long *port_mask;
|
|
int i, maxport, pn, nports = 0, ret = 0;
|
|
unsigned int m_port;
|
|
|
|
mutex_lock(&ctrl->port_lock);
|
|
list_for_each_entry(m_rt, &stream->master_list, stream_node) {
|
|
if (m_rt->direction == SDW_DATA_DIR_RX) {
|
|
maxport = ctrl->num_dout_ports;
|
|
port_mask = &ctrl->dout_port_mask;
|
|
} else {
|
|
maxport = ctrl->num_din_ports;
|
|
port_mask = &ctrl->din_port_mask;
|
|
}
|
|
|
|
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
|
|
slave = s_rt->slave;
|
|
list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
|
|
m_port = slave->m_port_map[p_rt->num];
|
|
/* Port numbers start from 1 - 14*/
|
|
if (m_port)
|
|
pn = m_port;
|
|
else
|
|
pn = find_first_zero_bit(port_mask, maxport);
|
|
|
|
if (pn > maxport) {
|
|
dev_err(ctrl->dev, "All ports busy\n");
|
|
ret = -EBUSY;
|
|
goto err;
|
|
}
|
|
set_bit(pn, port_mask);
|
|
pconfig[nports].num = pn;
|
|
pconfig[nports].ch_mask = p_rt->ch_mask;
|
|
nports++;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (direction == SNDRV_PCM_STREAM_CAPTURE)
|
|
sconfig.direction = SDW_DATA_DIR_TX;
|
|
else
|
|
sconfig.direction = SDW_DATA_DIR_RX;
|
|
|
|
/* hw parameters wil be ignored as we only support PDM */
|
|
sconfig.ch_count = 1;
|
|
sconfig.frame_rate = params_rate(params);
|
|
sconfig.type = stream->type;
|
|
sconfig.bps = 1;
|
|
sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
|
|
nports, stream);
|
|
err:
|
|
if (ret) {
|
|
for (i = 0; i < nports; i++)
|
|
clear_bit(pconfig[i].num, port_mask);
|
|
}
|
|
|
|
mutex_unlock(&ctrl->port_lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
|
|
struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
|
|
int ret;
|
|
|
|
ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
|
|
substream->stream);
|
|
if (ret)
|
|
qcom_swrm_stream_free_ports(ctrl, sruntime);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
|
|
struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
|
|
|
|
qcom_swrm_stream_free_ports(ctrl, sruntime);
|
|
sdw_stream_remove_master(&ctrl->bus, sruntime);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
|
|
void *stream, int direction)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
|
|
|
|
ctrl->sruntime[dai->id] = stream;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
|
|
|
|
return ctrl->sruntime[dai->id];
|
|
}
|
|
|
|
static int qcom_swrm_startup(struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
|
|
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
|
struct sdw_stream_runtime *sruntime;
|
|
struct snd_soc_dai *codec_dai;
|
|
int ret, i;
|
|
|
|
ret = pm_runtime_resume_and_get(ctrl->dev);
|
|
if (ret < 0 && ret != -EACCES) {
|
|
dev_err_ratelimited(ctrl->dev,
|
|
"pm_runtime_resume_and_get failed in %s, ret %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
sruntime = sdw_alloc_stream(dai->name);
|
|
if (!sruntime)
|
|
return -ENOMEM;
|
|
|
|
ctrl->sruntime[dai->id] = sruntime;
|
|
|
|
for_each_rtd_codec_dais(rtd, i, codec_dai) {
|
|
ret = snd_soc_dai_set_stream(codec_dai, sruntime,
|
|
substream->stream);
|
|
if (ret < 0 && ret != -ENOTSUPP) {
|
|
dev_err(dai->dev, "Failed to set sdw stream on %s\n",
|
|
codec_dai->name);
|
|
sdw_release_stream(sruntime);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
|
|
|
|
sdw_release_stream(ctrl->sruntime[dai->id]);
|
|
ctrl->sruntime[dai->id] = NULL;
|
|
pm_runtime_mark_last_busy(ctrl->dev);
|
|
pm_runtime_put_autosuspend(ctrl->dev);
|
|
|
|
}
|
|
|
|
static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
|
|
.hw_params = qcom_swrm_hw_params,
|
|
.hw_free = qcom_swrm_hw_free,
|
|
.startup = qcom_swrm_startup,
|
|
.shutdown = qcom_swrm_shutdown,
|
|
.set_stream = qcom_swrm_set_sdw_stream,
|
|
.get_stream = qcom_swrm_get_sdw_stream,
|
|
};
|
|
|
|
static const struct snd_soc_component_driver qcom_swrm_dai_component = {
|
|
.name = "soundwire",
|
|
};
|
|
|
|
static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
|
|
{
|
|
int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
|
|
struct snd_soc_dai_driver *dais;
|
|
struct snd_soc_pcm_stream *stream;
|
|
struct device *dev = ctrl->dev;
|
|
int i;
|
|
|
|
/* PDM dais are only tested for now */
|
|
dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
|
|
if (!dais)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < num_dais; i++) {
|
|
dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
|
|
if (!dais[i].name)
|
|
return -ENOMEM;
|
|
|
|
if (i < ctrl->num_dout_ports)
|
|
stream = &dais[i].playback;
|
|
else
|
|
stream = &dais[i].capture;
|
|
|
|
stream->channels_min = 1;
|
|
stream->channels_max = 1;
|
|
stream->rates = SNDRV_PCM_RATE_48000;
|
|
stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
|
|
|
|
dais[i].ops = &qcom_swrm_pdm_dai_ops;
|
|
dais[i].id = i;
|
|
}
|
|
|
|
return devm_snd_soc_register_component(ctrl->dev,
|
|
&qcom_swrm_dai_component,
|
|
dais, num_dais);
|
|
}
|
|
|
|
static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
|
|
{
|
|
struct device_node *np = ctrl->dev->of_node;
|
|
u8 off1[QCOM_SDW_MAX_PORTS];
|
|
u8 off2[QCOM_SDW_MAX_PORTS];
|
|
u8 si[QCOM_SDW_MAX_PORTS];
|
|
u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
|
|
u8 hstart[QCOM_SDW_MAX_PORTS];
|
|
u8 hstop[QCOM_SDW_MAX_PORTS];
|
|
u8 word_length[QCOM_SDW_MAX_PORTS];
|
|
u8 blk_group_count[QCOM_SDW_MAX_PORTS];
|
|
u8 lane_control[QCOM_SDW_MAX_PORTS];
|
|
int i, ret, nports, val;
|
|
|
|
ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
|
|
|
|
ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
|
|
ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
|
|
|
|
ret = of_property_read_u32(np, "qcom,din-ports", &val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (val > ctrl->num_din_ports)
|
|
return -EINVAL;
|
|
|
|
ctrl->num_din_ports = val;
|
|
|
|
ret = of_property_read_u32(np, "qcom,dout-ports", &val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (val > ctrl->num_dout_ports)
|
|
return -EINVAL;
|
|
|
|
ctrl->num_dout_ports = val;
|
|
|
|
nports = ctrl->num_dout_ports + ctrl->num_din_ports;
|
|
/* Valid port numbers are from 1-14, so mask out port 0 explicitly */
|
|
set_bit(0, &ctrl->dout_port_mask);
|
|
set_bit(0, &ctrl->din_port_mask);
|
|
|
|
ret = of_property_read_u8_array(np, "qcom,ports-offset1",
|
|
off1, nports);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = of_property_read_u8_array(np, "qcom,ports-offset2",
|
|
off2, nports);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
|
|
si, nports);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
|
|
bp_mode, nports);
|
|
if (ret) {
|
|
if (ctrl->version <= 0x01030000)
|
|
memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
|
|
else
|
|
return ret;
|
|
}
|
|
|
|
memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
|
|
of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
|
|
|
|
memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
|
|
of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
|
|
|
|
memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
|
|
of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
|
|
|
|
memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
|
|
of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
|
|
|
|
memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
|
|
of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
|
|
|
|
for (i = 0; i < nports; i++) {
|
|
/* Valid port number range is from 1-14 */
|
|
ctrl->pconfig[i + 1].si = si[i];
|
|
ctrl->pconfig[i + 1].off1 = off1[i];
|
|
ctrl->pconfig[i + 1].off2 = off2[i];
|
|
ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
|
|
ctrl->pconfig[i + 1].hstart = hstart[i];
|
|
ctrl->pconfig[i + 1].hstop = hstop[i];
|
|
ctrl->pconfig[i + 1].word_length = word_length[i];
|
|
ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
|
|
ctrl->pconfig[i + 1].lane_control = lane_control[i];
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
static int swrm_reg_show(struct seq_file *s_file, void *data)
|
|
{
|
|
struct qcom_swrm_ctrl *swrm = s_file->private;
|
|
int reg, reg_val, ret;
|
|
|
|
ret = pm_runtime_resume_and_get(swrm->dev);
|
|
if (ret < 0 && ret != -EACCES) {
|
|
dev_err_ratelimited(swrm->dev,
|
|
"pm_runtime_resume_and_get failed in %s, ret %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
|
|
swrm->reg_read(swrm, reg, ®_val);
|
|
seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
|
|
}
|
|
pm_runtime_mark_last_busy(swrm->dev);
|
|
pm_runtime_put_autosuspend(swrm->dev);
|
|
|
|
|
|
return 0;
|
|
}
|
|
DEFINE_SHOW_ATTRIBUTE(swrm_reg);
|
|
#endif
|
|
|
|
static int qcom_swrm_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct sdw_master_prop *prop;
|
|
struct sdw_bus_params *params;
|
|
struct qcom_swrm_ctrl *ctrl;
|
|
const struct qcom_swrm_data *data;
|
|
int ret;
|
|
u32 val;
|
|
|
|
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
|
|
if (!ctrl)
|
|
return -ENOMEM;
|
|
|
|
data = of_device_get_match_data(dev);
|
|
ctrl->rows_index = sdw_find_row_index(data->default_rows);
|
|
ctrl->cols_index = sdw_find_col_index(data->default_cols);
|
|
#if IS_REACHABLE(CONFIG_SLIMBUS)
|
|
if (dev->parent->bus == &slimbus_bus) {
|
|
#else
|
|
if (false) {
|
|
#endif
|
|
ctrl->reg_read = qcom_swrm_ahb_reg_read;
|
|
ctrl->reg_write = qcom_swrm_ahb_reg_write;
|
|
ctrl->regmap = dev_get_regmap(dev->parent, NULL);
|
|
if (!ctrl->regmap)
|
|
return -EINVAL;
|
|
} else {
|
|
ctrl->reg_read = qcom_swrm_cpu_reg_read;
|
|
ctrl->reg_write = qcom_swrm_cpu_reg_write;
|
|
ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(ctrl->mmio))
|
|
return PTR_ERR(ctrl->mmio);
|
|
}
|
|
|
|
if (data->sw_clk_gate_required) {
|
|
ctrl->audio_cgcr = devm_reset_control_get_exclusive(dev, "swr_audio_cgcr");
|
|
if (IS_ERR_OR_NULL(ctrl->audio_cgcr)) {
|
|
dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
|
|
ret = PTR_ERR(ctrl->audio_cgcr);
|
|
goto err_init;
|
|
}
|
|
}
|
|
|
|
ctrl->irq = of_irq_get(dev->of_node, 0);
|
|
if (ctrl->irq < 0) {
|
|
ret = ctrl->irq;
|
|
goto err_init;
|
|
}
|
|
|
|
ctrl->hclk = devm_clk_get(dev, "iface");
|
|
if (IS_ERR(ctrl->hclk)) {
|
|
ret = PTR_ERR(ctrl->hclk);
|
|
goto err_init;
|
|
}
|
|
|
|
clk_prepare_enable(ctrl->hclk);
|
|
|
|
ctrl->dev = dev;
|
|
dev_set_drvdata(&pdev->dev, ctrl);
|
|
mutex_init(&ctrl->port_lock);
|
|
init_completion(&ctrl->broadcast);
|
|
init_completion(&ctrl->enumeration);
|
|
|
|
ctrl->bus.ops = &qcom_swrm_ops;
|
|
ctrl->bus.port_ops = &qcom_swrm_port_ops;
|
|
ctrl->bus.compute_params = &qcom_swrm_compute_params;
|
|
ctrl->bus.clk_stop_timeout = 300;
|
|
|
|
ret = qcom_swrm_get_port_config(ctrl);
|
|
if (ret)
|
|
goto err_clk;
|
|
|
|
params = &ctrl->bus.params;
|
|
params->max_dr_freq = DEFAULT_CLK_FREQ;
|
|
params->curr_dr_freq = DEFAULT_CLK_FREQ;
|
|
params->col = data->default_cols;
|
|
params->row = data->default_rows;
|
|
ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
|
|
params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
|
|
params->next_bank = !params->curr_bank;
|
|
|
|
prop = &ctrl->bus.prop;
|
|
prop->max_clk_freq = DEFAULT_CLK_FREQ;
|
|
prop->num_clk_gears = 0;
|
|
prop->num_clk_freq = MAX_FREQ_NUM;
|
|
prop->clk_freq = &qcom_swrm_freq_tbl[0];
|
|
prop->default_col = data->default_cols;
|
|
prop->default_row = data->default_rows;
|
|
|
|
ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
|
|
|
|
ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
|
|
qcom_swrm_irq_handler,
|
|
IRQF_TRIGGER_RISING |
|
|
IRQF_ONESHOT,
|
|
"soundwire", ctrl);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to request soundwire irq\n");
|
|
goto err_clk;
|
|
}
|
|
|
|
ctrl->wake_irq = of_irq_get(dev->of_node, 1);
|
|
if (ctrl->wake_irq > 0) {
|
|
ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
|
|
qcom_swrm_wake_irq_handler,
|
|
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
|
|
"swr_wake_irq", ctrl);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to request soundwire wake irq\n");
|
|
goto err_init;
|
|
}
|
|
}
|
|
|
|
ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to register Soundwire controller (%d)\n",
|
|
ret);
|
|
goto err_clk;
|
|
}
|
|
|
|
qcom_swrm_init(ctrl);
|
|
wait_for_completion_timeout(&ctrl->enumeration,
|
|
msecs_to_jiffies(TIMEOUT_MS));
|
|
ret = qcom_swrm_register_dais(ctrl);
|
|
if (ret)
|
|
goto err_master_add;
|
|
|
|
dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
|
|
(ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
|
|
ctrl->version & 0xffff);
|
|
|
|
pm_runtime_set_autosuspend_delay(dev, 3000);
|
|
pm_runtime_use_autosuspend(dev);
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
|
|
/* Clk stop is not supported on WSA Soundwire masters */
|
|
if (ctrl->version <= 0x01030000) {
|
|
ctrl->clock_stop_not_supported = true;
|
|
} else {
|
|
ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
|
|
if (val == MASTER_ID_WSA)
|
|
ctrl->clock_stop_not_supported = true;
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
|
|
debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
|
|
&swrm_reg_fops);
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
err_master_add:
|
|
sdw_bus_master_delete(&ctrl->bus);
|
|
err_clk:
|
|
clk_disable_unprepare(ctrl->hclk);
|
|
err_init:
|
|
return ret;
|
|
}
|
|
|
|
static int qcom_swrm_remove(struct platform_device *pdev)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
|
|
|
|
sdw_bus_master_delete(&ctrl->bus);
|
|
clk_disable_unprepare(ctrl->hclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm)
|
|
{
|
|
int retry = SWRM_LINK_STATUS_RETRY_CNT;
|
|
int comp_sts;
|
|
|
|
do {
|
|
swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
|
|
|
|
if (comp_sts & SWRM_FRM_GEN_ENABLED)
|
|
return true;
|
|
|
|
usleep_range(500, 510);
|
|
} while (retry--);
|
|
|
|
dev_err(swrm->dev, "%s: link status not %s\n", __func__,
|
|
comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
|
|
|
|
return false;
|
|
}
|
|
|
|
static int __maybe_unused swrm_runtime_resume(struct device *dev)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
if (ctrl->wake_irq > 0) {
|
|
if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
|
|
disable_irq_nosync(ctrl->wake_irq);
|
|
}
|
|
|
|
clk_prepare_enable(ctrl->hclk);
|
|
|
|
if (ctrl->clock_stop_not_supported) {
|
|
reinit_completion(&ctrl->enumeration);
|
|
ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
|
|
usleep_range(100, 105);
|
|
|
|
qcom_swrm_init(ctrl);
|
|
|
|
usleep_range(100, 105);
|
|
if (!swrm_wait_for_frame_gen_enabled(ctrl))
|
|
dev_err(ctrl->dev, "link failed to connect\n");
|
|
|
|
/* wait for hw enumeration to complete */
|
|
wait_for_completion_timeout(&ctrl->enumeration,
|
|
msecs_to_jiffies(TIMEOUT_MS));
|
|
qcom_swrm_get_device_status(ctrl);
|
|
sdw_handle_slave_status(&ctrl->bus, ctrl->status);
|
|
} else {
|
|
reset_control_reset(ctrl->audio_cgcr);
|
|
|
|
ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
|
|
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
|
|
SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
|
|
|
|
ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
|
|
ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
|
|
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
|
|
|
|
usleep_range(100, 105);
|
|
if (!swrm_wait_for_frame_gen_enabled(ctrl))
|
|
dev_err(ctrl->dev, "link failed to connect\n");
|
|
|
|
ret = sdw_bus_exit_clk_stop(&ctrl->bus);
|
|
if (ret < 0)
|
|
dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused swrm_runtime_suspend(struct device *dev)
|
|
{
|
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
if (!ctrl->clock_stop_not_supported) {
|
|
/* Mask bus clash interrupt */
|
|
ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
|
|
ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
|
|
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
|
|
/* Prepare slaves for clock stop */
|
|
ret = sdw_bus_prep_clk_stop(&ctrl->bus);
|
|
if (ret < 0 && ret != -ENODATA) {
|
|
dev_err(dev, "prepare clock stop failed %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = sdw_bus_clk_stop(&ctrl->bus);
|
|
if (ret < 0 && ret != -ENODATA) {
|
|
dev_err(dev, "bus clock stop failed %d", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
clk_disable_unprepare(ctrl->hclk);
|
|
|
|
usleep_range(300, 305);
|
|
|
|
if (ctrl->wake_irq > 0) {
|
|
if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
|
|
enable_irq(ctrl->wake_irq);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops swrm_dev_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
|
|
};
|
|
|
|
static const struct of_device_id qcom_swrm_of_match[] = {
|
|
{ .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
|
|
{ .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
|
|
{ .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
|
|
{/* sentinel */},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
|
|
|
|
static struct platform_driver qcom_swrm_driver = {
|
|
.probe = &qcom_swrm_probe,
|
|
.remove = &qcom_swrm_remove,
|
|
.driver = {
|
|
.name = "qcom-soundwire",
|
|
.of_match_table = qcom_swrm_of_match,
|
|
.pm = &swrm_dev_pm_ops,
|
|
}
|
|
};
|
|
module_platform_driver(qcom_swrm_driver);
|
|
|
|
MODULE_DESCRIPTION("Qualcomm soundwire driver");
|
|
MODULE_LICENSE("GPL v2");
|