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![Mauro Carvalho Chehab](/assets/img/avatar_default.png)
The Hisilicon 6421v600 SPMI driver is ready for mainstream. So, move it from staging. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/35b9f9169889c1f4d51eff8bf2035450c9e02576.1624606660.git.mchehab+huawei@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
367 lines
9.7 KiB
C
367 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/spmi.h>
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/*
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* SPMI register addr
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*/
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#define SPMI_CHANNEL_OFFSET 0x0300
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#define SPMI_SLAVE_OFFSET 0x20
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#define SPMI_APB_SPMI_CMD_BASE_ADDR 0x0100
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#define SPMI_APB_SPMI_WDATA0_BASE_ADDR 0x0104
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#define SPMI_APB_SPMI_WDATA1_BASE_ADDR 0x0108
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#define SPMI_APB_SPMI_WDATA2_BASE_ADDR 0x010c
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#define SPMI_APB_SPMI_WDATA3_BASE_ADDR 0x0110
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#define SPMI_APB_SPMI_STATUS_BASE_ADDR 0x0200
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#define SPMI_APB_SPMI_RDATA0_BASE_ADDR 0x0204
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#define SPMI_APB_SPMI_RDATA1_BASE_ADDR 0x0208
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#define SPMI_APB_SPMI_RDATA2_BASE_ADDR 0x020c
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#define SPMI_APB_SPMI_RDATA3_BASE_ADDR 0x0210
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#define SPMI_PER_DATAREG_BYTE 4
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/*
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* SPMI cmd register
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*/
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#define SPMI_APB_SPMI_CMD_EN BIT(31)
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#define SPMI_APB_SPMI_CMD_TYPE_OFFSET 24
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#define SPMI_APB_SPMI_CMD_LENGTH_OFFSET 20
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#define SPMI_APB_SPMI_CMD_SLAVEID_OFFSET 16
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#define SPMI_APB_SPMI_CMD_ADDR_OFFSET 0
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/* Command Opcodes */
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enum spmi_controller_cmd_op_code {
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SPMI_CMD_REG_ZERO_WRITE = 0,
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SPMI_CMD_REG_WRITE = 1,
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SPMI_CMD_REG_READ = 2,
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SPMI_CMD_EXT_REG_WRITE = 3,
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SPMI_CMD_EXT_REG_READ = 4,
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SPMI_CMD_EXT_REG_WRITE_L = 5,
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SPMI_CMD_EXT_REG_READ_L = 6,
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SPMI_CMD_REG_RESET = 7,
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SPMI_CMD_REG_SLEEP = 8,
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SPMI_CMD_REG_SHUTDOWN = 9,
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SPMI_CMD_REG_WAKEUP = 10,
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};
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/*
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* SPMI status register
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*/
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#define SPMI_APB_TRANS_DONE BIT(0)
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#define SPMI_APB_TRANS_FAIL BIT(2)
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/* Command register fields */
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#define SPMI_CONTROLLER_CMD_MAX_BYTE_COUNT 16
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/* Maximum number of support PMIC peripherals */
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#define SPMI_CONTROLLER_TIMEOUT_US 1000
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#define SPMI_CONTROLLER_MAX_TRANS_BYTES 16
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struct spmi_controller_dev {
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struct spmi_controller *controller;
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struct device *dev;
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void __iomem *base;
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spinlock_t lock;
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u32 channel;
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};
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static int spmi_controller_wait_for_done(struct device *dev,
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struct spmi_controller_dev *ctrl_dev,
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void __iomem *base, u8 sid, u16 addr)
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{
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u32 timeout = SPMI_CONTROLLER_TIMEOUT_US;
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u32 status, offset;
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offset = SPMI_APB_SPMI_STATUS_BASE_ADDR;
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offset += SPMI_CHANNEL_OFFSET * ctrl_dev->channel + SPMI_SLAVE_OFFSET * sid;
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do {
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status = readl(base + offset);
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if (status & SPMI_APB_TRANS_DONE) {
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if (status & SPMI_APB_TRANS_FAIL) {
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dev_err(dev, "%s: transaction failed (0x%x)\n",
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__func__, status);
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return -EIO;
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}
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dev_dbg(dev, "%s: status 0x%x\n", __func__, status);
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return 0;
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}
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udelay(1);
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} while (timeout--);
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dev_err(dev, "%s: timeout, status 0x%x\n", __func__, status);
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return -ETIMEDOUT;
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}
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static int spmi_read_cmd(struct spmi_controller *ctrl,
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u8 opc, u8 slave_id, u16 slave_addr, u8 *__buf, size_t bc)
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{
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struct spmi_controller_dev *spmi_controller = dev_get_drvdata(&ctrl->dev);
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u32 chnl_ofst = SPMI_CHANNEL_OFFSET * spmi_controller->channel;
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unsigned long flags;
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u8 *buf = __buf;
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u32 cmd, data;
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int rc;
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u8 op_code, i;
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if (bc > SPMI_CONTROLLER_MAX_TRANS_BYTES) {
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dev_err(&ctrl->dev,
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"spmi_controller supports 1..%d bytes per trans, but:%zu requested\n",
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SPMI_CONTROLLER_MAX_TRANS_BYTES, bc);
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return -EINVAL;
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}
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switch (opc) {
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case SPMI_CMD_READ:
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op_code = SPMI_CMD_REG_READ;
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break;
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case SPMI_CMD_EXT_READ:
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op_code = SPMI_CMD_EXT_REG_READ;
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break;
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case SPMI_CMD_EXT_READL:
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op_code = SPMI_CMD_EXT_REG_READ_L;
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break;
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default:
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dev_err(&ctrl->dev, "invalid read cmd 0x%x\n", opc);
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return -EINVAL;
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}
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cmd = SPMI_APB_SPMI_CMD_EN |
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(op_code << SPMI_APB_SPMI_CMD_TYPE_OFFSET) |
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((bc - 1) << SPMI_APB_SPMI_CMD_LENGTH_OFFSET) |
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((slave_id & 0xf) << SPMI_APB_SPMI_CMD_SLAVEID_OFFSET) | /* slvid */
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((slave_addr & 0xffff) << SPMI_APB_SPMI_CMD_ADDR_OFFSET); /* slave_addr */
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spin_lock_irqsave(&spmi_controller->lock, flags);
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writel(cmd, spmi_controller->base + chnl_ofst + SPMI_APB_SPMI_CMD_BASE_ADDR);
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rc = spmi_controller_wait_for_done(&ctrl->dev, spmi_controller,
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spmi_controller->base, slave_id, slave_addr);
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if (rc)
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goto done;
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for (i = 0; bc > i * SPMI_PER_DATAREG_BYTE; i++) {
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data = readl(spmi_controller->base + chnl_ofst +
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SPMI_SLAVE_OFFSET * slave_id +
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SPMI_APB_SPMI_RDATA0_BASE_ADDR +
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i * SPMI_PER_DATAREG_BYTE);
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data = be32_to_cpu((__be32 __force)data);
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if ((bc - i * SPMI_PER_DATAREG_BYTE) >> 2) {
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memcpy(buf, &data, sizeof(data));
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buf += sizeof(data);
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} else {
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memcpy(buf, &data, bc % SPMI_PER_DATAREG_BYTE);
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buf += (bc % SPMI_PER_DATAREG_BYTE);
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}
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}
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done:
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spin_unlock_irqrestore(&spmi_controller->lock, flags);
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if (rc)
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dev_err(&ctrl->dev,
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"spmi read wait timeout op:0x%x slave_id:%d slave_addr:0x%x bc:%zu\n",
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opc, slave_id, slave_addr, bc + 1);
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else
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dev_dbg(&ctrl->dev, "%s: id:%d slave_addr:0x%x, read value: %*ph\n",
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__func__, slave_id, slave_addr, (int)bc, __buf);
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return rc;
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}
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static int spmi_write_cmd(struct spmi_controller *ctrl,
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u8 opc, u8 slave_id, u16 slave_addr, const u8 *__buf, size_t bc)
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{
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struct spmi_controller_dev *spmi_controller = dev_get_drvdata(&ctrl->dev);
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u32 chnl_ofst = SPMI_CHANNEL_OFFSET * spmi_controller->channel;
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const u8 *buf = __buf;
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unsigned long flags;
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u32 cmd, data;
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int rc;
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u8 op_code, i;
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if (bc > SPMI_CONTROLLER_MAX_TRANS_BYTES) {
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dev_err(&ctrl->dev,
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"spmi_controller supports 1..%d bytes per trans, but:%zu requested\n",
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SPMI_CONTROLLER_MAX_TRANS_BYTES, bc);
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return -EINVAL;
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}
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switch (opc) {
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case SPMI_CMD_WRITE:
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op_code = SPMI_CMD_REG_WRITE;
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break;
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case SPMI_CMD_EXT_WRITE:
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op_code = SPMI_CMD_EXT_REG_WRITE;
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break;
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case SPMI_CMD_EXT_WRITEL:
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op_code = SPMI_CMD_EXT_REG_WRITE_L;
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break;
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default:
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dev_err(&ctrl->dev, "invalid write cmd 0x%x\n", opc);
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return -EINVAL;
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}
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cmd = SPMI_APB_SPMI_CMD_EN |
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(op_code << SPMI_APB_SPMI_CMD_TYPE_OFFSET) |
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((bc - 1) << SPMI_APB_SPMI_CMD_LENGTH_OFFSET) |
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((slave_id & 0xf) << SPMI_APB_SPMI_CMD_SLAVEID_OFFSET) |
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((slave_addr & 0xffff) << SPMI_APB_SPMI_CMD_ADDR_OFFSET);
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/* Write data to FIFOs */
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spin_lock_irqsave(&spmi_controller->lock, flags);
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for (i = 0; bc > i * SPMI_PER_DATAREG_BYTE; i++) {
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data = 0;
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if ((bc - i * SPMI_PER_DATAREG_BYTE) >> 2) {
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memcpy(&data, buf, sizeof(data));
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buf += sizeof(data);
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} else {
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memcpy(&data, buf, bc % SPMI_PER_DATAREG_BYTE);
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buf += (bc % SPMI_PER_DATAREG_BYTE);
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}
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writel((u32 __force)cpu_to_be32(data),
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spmi_controller->base + chnl_ofst +
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SPMI_APB_SPMI_WDATA0_BASE_ADDR +
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SPMI_PER_DATAREG_BYTE * i);
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}
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/* Start the transaction */
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writel(cmd, spmi_controller->base + chnl_ofst + SPMI_APB_SPMI_CMD_BASE_ADDR);
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rc = spmi_controller_wait_for_done(&ctrl->dev, spmi_controller,
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spmi_controller->base, slave_id,
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slave_addr);
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spin_unlock_irqrestore(&spmi_controller->lock, flags);
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if (rc)
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dev_err(&ctrl->dev, "spmi write wait timeout op:0x%x slave_id:%d slave_addr:0x%x bc:%zu\n",
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opc, slave_id, slave_addr, bc);
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else
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dev_dbg(&ctrl->dev, "%s: id:%d slave_addr:0x%x, wrote value: %*ph\n",
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__func__, slave_id, slave_addr, (int)bc, __buf);
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return rc;
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}
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static int spmi_controller_probe(struct platform_device *pdev)
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{
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struct spmi_controller_dev *spmi_controller;
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struct spmi_controller *ctrl;
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struct resource *iores;
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int ret;
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ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*spmi_controller));
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if (!ctrl) {
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dev_err(&pdev->dev, "can not allocate spmi_controller data\n");
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return -ENOMEM;
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}
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spmi_controller = spmi_controller_get_drvdata(ctrl);
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spmi_controller->controller = ctrl;
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iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!iores) {
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dev_err(&pdev->dev, "can not get resource!\n");
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ret = -EINVAL;
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goto err_put_controller;
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}
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spmi_controller->base = devm_ioremap(&pdev->dev, iores->start,
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resource_size(iores));
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if (!spmi_controller->base) {
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dev_err(&pdev->dev, "can not remap base addr!\n");
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ret = -EADDRNOTAVAIL;
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goto err_put_controller;
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}
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ret = of_property_read_u32(pdev->dev.of_node, "hisilicon,spmi-channel",
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&spmi_controller->channel);
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if (ret) {
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dev_err(&pdev->dev, "can not get channel\n");
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ret = -ENODEV;
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goto err_put_controller;
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}
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platform_set_drvdata(pdev, spmi_controller);
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dev_set_drvdata(&ctrl->dev, spmi_controller);
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spin_lock_init(&spmi_controller->lock);
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ctrl->nr = spmi_controller->channel;
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ctrl->dev.parent = pdev->dev.parent;
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ctrl->dev.of_node = of_node_get(pdev->dev.of_node);
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/* Callbacks */
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ctrl->read_cmd = spmi_read_cmd;
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ctrl->write_cmd = spmi_write_cmd;
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ret = spmi_controller_add(ctrl);
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if (ret) {
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dev_err(&pdev->dev, "spmi_controller_add failed with error %d!\n", ret);
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goto err_put_controller;
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}
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return 0;
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err_put_controller:
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spmi_controller_put(ctrl);
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return ret;
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}
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static int spmi_del_controller(struct platform_device *pdev)
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{
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struct spmi_controller *ctrl = platform_get_drvdata(pdev);
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spmi_controller_remove(ctrl);
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spmi_controller_put(ctrl);
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return 0;
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}
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static const struct of_device_id spmi_controller_match_table[] = {
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{
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.compatible = "hisilicon,kirin970-spmi-controller",
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, spmi_controller_match_table);
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static struct platform_driver spmi_controller_driver = {
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.probe = spmi_controller_probe,
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.remove = spmi_del_controller,
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.driver = {
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.name = "hisi_spmi_controller",
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.of_match_table = spmi_controller_match_table,
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},
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};
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static int __init spmi_controller_init(void)
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{
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return platform_driver_register(&spmi_controller_driver);
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}
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postcore_initcall(spmi_controller_init);
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static void __exit spmi_controller_exit(void)
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{
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platform_driver_unregister(&spmi_controller_driver);
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}
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module_exit(spmi_controller_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_VERSION("1.0");
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MODULE_ALIAS("platform:spmi_controller");
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