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dfd2edccfd
Panel drivers can send DSI commands in panel's prepare(), which happens before the bridge's enable() is called. The OMAP DSI driver currently only sets up the DSI interface at bridge's enable(), so prepare() cannot be used to send DSI commands. This patch fixes the issue by making it possible to enable the DSI interface any time a command is about to be sent. Disabling the interface is be done via delayed work. Clarifications for the delayed disable work and the panel doing DSI transactions: bridge_enable: If the disable callback is called just before bridge_enable takes the dsi_bus_lock, no problem, bridge_enable just enables the interface again. If the callback is ran just after bridge_enable's dsi_bus_unlock, no problem, dsi->video_enabled == true so the callback does nothing. bridge_disable: similar to bridge-enable, the callback won't do anything if video_enabled == true, and after bridge-disable has turned the video and the interface off, there's nothing to do for the callback. omap_dsi_host_detach: this is called when the panel does mipi_dsi_detach(), and we expect the panel to _not_ do any DSI transactions after (or during) mipi_dsi_detatch(), so there are no race conditions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201215104657.802264-85-tomi.valkeinen@ti.com
456 lines
12 KiB
C
456 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*/
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#ifndef __OMAP_DRM_DSS_DSI_H
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#define __OMAP_DRM_DSS_DSI_H
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#include <drm/drm_mipi_dsi.h>
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struct dsi_reg {
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u16 module;
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u16 idx;
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};
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#define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
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/* DSI Protocol Engine */
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#define DSI_PROTO 0
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#define DSI_PROTO_SZ 0x200
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#define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
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#define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
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#define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
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#define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
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#define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
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#define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
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#define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
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#define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
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#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
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#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
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#define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
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#define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
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#define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
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#define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
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#define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
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#define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
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#define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
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#define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
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#define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
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#define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
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#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
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#define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
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#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
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#define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
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#define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
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#define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
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#define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
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#define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
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#define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
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#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
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#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
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#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
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#define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
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#define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
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/* DSIPHY_SCP */
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#define DSI_PHY 1
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#define DSI_PHY_OFFSET 0x200
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#define DSI_PHY_SZ 0x40
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#define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
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#define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
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#define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
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#define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
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#define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
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/* DSI_PLL_CTRL_SCP */
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#define DSI_PLL 2
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#define DSI_PLL_OFFSET 0x300
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#define DSI_PLL_SZ 0x20
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#define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
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#define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
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#define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
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#define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
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#define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
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/* Global interrupts */
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#define DSI_IRQ_VC0 (1 << 0)
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#define DSI_IRQ_VC1 (1 << 1)
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#define DSI_IRQ_VC2 (1 << 2)
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#define DSI_IRQ_VC3 (1 << 3)
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#define DSI_IRQ_WAKEUP (1 << 4)
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#define DSI_IRQ_RESYNC (1 << 5)
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#define DSI_IRQ_PLL_LOCK (1 << 7)
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#define DSI_IRQ_PLL_UNLOCK (1 << 8)
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#define DSI_IRQ_PLL_RECALL (1 << 9)
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#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
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#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
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#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
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#define DSI_IRQ_TE_TRIGGER (1 << 16)
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#define DSI_IRQ_ACK_TRIGGER (1 << 17)
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#define DSI_IRQ_SYNC_LOST (1 << 18)
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#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
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#define DSI_IRQ_TA_TIMEOUT (1 << 20)
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#define DSI_IRQ_ERROR_MASK \
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(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
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DSI_IRQ_TA_TIMEOUT)
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#define DSI_IRQ_CHANNEL_MASK 0xf
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/* Virtual channel interrupts */
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#define DSI_VC_IRQ_CS (1 << 0)
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#define DSI_VC_IRQ_ECC_CORR (1 << 1)
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#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
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#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
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#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
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#define DSI_VC_IRQ_BTA (1 << 5)
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#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
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#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
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#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
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#define DSI_VC_IRQ_ERROR_MASK \
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(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
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DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
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DSI_VC_IRQ_FIFO_TX_UDF)
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/* ComplexIO interrupts */
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#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
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#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
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#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
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#define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
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#define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
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#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
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#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
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#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
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#define DSI_CIO_IRQ_ERRESC4 (1 << 8)
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#define DSI_CIO_IRQ_ERRESC5 (1 << 9)
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#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
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#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
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#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
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#define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
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#define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
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#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
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#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
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#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
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#define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
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#define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
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#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
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#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
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#define DSI_CIO_IRQ_ERROR_MASK \
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(DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
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DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
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DSI_CIO_IRQ_ERRSYNCESC5 | \
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DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
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DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
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DSI_CIO_IRQ_ERRESC5 | \
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DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
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DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
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DSI_CIO_IRQ_ERRCONTROL5 | \
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DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
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DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
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DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
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DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
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DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
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enum omap_dss_dsi_mode {
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OMAP_DSS_DSI_CMD_MODE = 0,
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OMAP_DSS_DSI_VIDEO_MODE,
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};
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enum omap_dss_dsi_trans_mode {
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/* Sync Pulses: both sync start and end packets sent */
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OMAP_DSS_DSI_PULSE_MODE,
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/* Sync Events: only sync start packets sent */
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OMAP_DSS_DSI_EVENT_MODE,
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/* Burst: only sync start packets sent, pixels are time compressed */
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OMAP_DSS_DSI_BURST_MODE,
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};
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struct omap_dss_dsi_videomode_timings {
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unsigned long hsclk;
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unsigned int ndl;
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unsigned int bitspp;
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/* pixels */
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u16 hact;
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/* lines */
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u16 vact;
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/* DSI video mode blanking data */
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/* Unit: byte clock cycles */
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u16 hss;
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u16 hsa;
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u16 hse;
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u16 hfp;
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u16 hbp;
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/* Unit: line clocks */
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u16 vsa;
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u16 vfp;
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u16 vbp;
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/* DSI blanking modes */
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int blanking_mode;
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int hsa_blanking_mode;
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int hbp_blanking_mode;
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int hfp_blanking_mode;
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enum omap_dss_dsi_trans_mode trans_mode;
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int window_sync;
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};
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struct omap_dss_dsi_config {
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enum omap_dss_dsi_mode mode;
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enum mipi_dsi_pixel_format pixel_format;
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const struct videomode *vm;
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unsigned long hs_clk_min, hs_clk_max;
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unsigned long lp_clk_min, lp_clk_max;
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enum omap_dss_dsi_trans_mode trans_mode;
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};
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/* DSI PLL HSDIV indices */
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#define HSDIV_DISPC 0
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#define HSDIV_DSI 1
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#define DSI_MAX_NR_ISRS 2
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#define DSI_MAX_NR_LANES 5
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enum dsi_model {
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DSI_MODEL_OMAP3,
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DSI_MODEL_OMAP4,
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DSI_MODEL_OMAP5,
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};
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enum dsi_lane_function {
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DSI_LANE_UNUSED = 0,
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DSI_LANE_CLK,
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DSI_LANE_DATA1,
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DSI_LANE_DATA2,
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DSI_LANE_DATA3,
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DSI_LANE_DATA4,
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};
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struct dsi_lane_config {
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enum dsi_lane_function function;
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u8 polarity;
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};
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typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
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struct dsi_isr_data {
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omap_dsi_isr_t isr;
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void *arg;
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u32 mask;
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};
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enum fifo_size {
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DSI_FIFO_SIZE_0 = 0,
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DSI_FIFO_SIZE_32 = 1,
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DSI_FIFO_SIZE_64 = 2,
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DSI_FIFO_SIZE_96 = 3,
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DSI_FIFO_SIZE_128 = 4,
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};
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enum dsi_vc_source {
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DSI_VC_SOURCE_L4 = 0,
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DSI_VC_SOURCE_VP,
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};
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struct dsi_irq_stats {
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unsigned long last_reset;
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unsigned int irq_count;
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unsigned int dsi_irqs[32];
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unsigned int vc_irqs[4][32];
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unsigned int cio_irqs[32];
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};
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struct dsi_isr_tables {
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struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
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struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
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struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
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};
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struct dsi_lp_clock_info {
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unsigned long lp_clk;
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u16 lp_clk_div;
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};
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struct dsi_clk_calc_ctx {
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struct dsi_data *dsi;
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struct dss_pll *pll;
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/* inputs */
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const struct omap_dss_dsi_config *config;
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unsigned long req_pck_min, req_pck_nom, req_pck_max;
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/* outputs */
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struct dss_pll_clock_info dsi_cinfo;
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struct dispc_clock_info dispc_cinfo;
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struct dsi_lp_clock_info lp_cinfo;
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struct videomode vm;
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struct omap_dss_dsi_videomode_timings dsi_vm;
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};
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struct dsi_module_id_data {
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u32 address;
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int id;
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};
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enum dsi_quirks {
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DSI_QUIRK_PLL_PWR_BUG = (1 << 0), /* DSI-PLL power command 0x3 is not working */
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DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1),
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DSI_QUIRK_VC_OCP_WIDTH = (1 << 2),
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DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3),
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DSI_QUIRK_GNQ = (1 << 4),
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DSI_QUIRK_PHY_DCC = (1 << 5),
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};
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struct dsi_of_data {
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enum dsi_model model;
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const struct dss_pll_hw *pll_hw;
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const struct dsi_module_id_data *modules;
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unsigned int max_fck_freq;
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unsigned int max_pll_lpdiv;
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enum dsi_quirks quirks;
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};
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struct dsi_data {
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struct device *dev;
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void __iomem *proto_base;
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void __iomem *phy_base;
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void __iomem *pll_base;
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const struct dsi_of_data *data;
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int module_id;
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int irq;
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bool is_enabled;
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struct clk *dss_clk;
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struct regmap *syscon;
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struct dss_device *dss;
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struct mipi_dsi_host host;
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struct dispc_clock_info user_dispc_cinfo;
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struct dss_pll_clock_info user_dsi_cinfo;
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struct dsi_lp_clock_info user_lp_cinfo;
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struct dsi_lp_clock_info current_lp_cinfo;
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struct dss_pll pll;
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bool vdds_dsi_enabled;
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struct regulator *vdds_dsi_reg;
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struct mipi_dsi_device *dsidev;
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struct {
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enum dsi_vc_source source;
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enum fifo_size tx_fifo_size;
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enum fifo_size rx_fifo_size;
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} vc[4];
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struct mutex lock;
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struct semaphore bus_lock;
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spinlock_t irq_lock;
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struct dsi_isr_tables isr_tables;
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/* space for a copy used by the interrupt handler */
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struct dsi_isr_tables isr_tables_copy;
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int update_vc;
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#ifdef DSI_PERF_MEASURE
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unsigned int update_bytes;
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#endif
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/* external TE GPIO */
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struct gpio_desc *te_gpio;
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int te_irq;
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struct delayed_work te_timeout_work;
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atomic_t do_ext_te_update;
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bool te_enabled;
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bool iface_enabled;
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bool video_enabled;
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struct delayed_work framedone_timeout_work;
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#ifdef DSI_CATCH_MISSING_TE
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struct timer_list te_timer;
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#endif
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unsigned long cache_req_pck;
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unsigned long cache_clk_freq;
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struct dss_pll_clock_info cache_cinfo;
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u32 errors;
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spinlock_t errors_lock;
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#ifdef DSI_PERF_MEASURE
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ktime_t perf_setup_time;
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ktime_t perf_start_time;
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#endif
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int debug_read;
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int debug_write;
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struct {
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struct dss_debugfs_entry *irqs;
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struct dss_debugfs_entry *regs;
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struct dss_debugfs_entry *clks;
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} debugfs;
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#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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spinlock_t irq_stats_lock;
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struct dsi_irq_stats irq_stats;
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#endif
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unsigned int num_lanes_supported;
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unsigned int line_buffer_size;
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struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
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unsigned int num_lanes_used;
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unsigned int scp_clk_refcount;
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struct omap_dss_dsi_config config;
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struct dss_lcd_mgr_config mgr_config;
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struct videomode vm;
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enum mipi_dsi_pixel_format pix_fmt;
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enum omap_dss_dsi_mode mode;
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struct omap_dss_dsi_videomode_timings vm_timings;
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struct omap_dss_device output;
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struct drm_bridge bridge;
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struct delayed_work dsi_disable_work;
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};
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struct dsi_packet_sent_handler_data {
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struct dsi_data *dsi;
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struct completion *completion;
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};
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#endif /* __OMAP_DRM_DSS_DSI_H */
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