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![Vladimir Zapolskiy](/assets/img/avatar_default.png)
If common clock framework is configured, the driver generates a warning, which is fixed by this change: WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:727 clk_core_enable+0x2c/0xa4() Modules linked in: CPU: 0 PID: 1 Comm: swapper Not tainted 4.3.0-rc2+ #201 Hardware name: LPC32XX SoC (Flattened Device Tree) Backtrace: [<>] (dump_backtrace) from [<>] (show_stack+0x18/0x1c) [<>] (show_stack) from [<>] (dump_stack+0x20/0x28) [<>] (dump_stack) from [<>] (warn_slowpath_common+0x90/0xb8) [<>] (warn_slowpath_common) from [<>] (warn_slowpath_null+0x24/0x2c) [<>] (warn_slowpath_null) from [<>] (clk_core_enable+0x2c/0xa4) [<>] (clk_core_enable) from [<>] (clk_enable+0x24/0x38) [<>] (clk_enable) from [<>] (lpc32xx_nand_probe+0x290/0x568) [<>] (lpc32xx_nand_probe) from [<>] (platform_drv_probe+0x50/0xa0) [<>] (platform_drv_probe) from [<>] (driver_probe_device+0x18c/0x408) [<>] (driver_probe_device) from [<>] (__driver_attach+0x70/0x94) [<>] (__driver_attach) from [<>] (bus_for_each_dev+0x74/0x98) [<>] (bus_for_each_dev) from [<>] (driver_attach+0x20/0x28) [<>] (driver_attach) from [<>] (bus_add_driver+0x11c/0x248) [<>] (bus_add_driver) from [<>] (driver_register+0xa4/0xe8) [<>] (driver_register) from [<>] (__platform_driver_register+0x50/0x64) [<>] (__platform_driver_register) from [<>] (lpc32xx_nand_driver_init+0x18/0x20) [<>] (lpc32xx_nand_driver_init) from [<>] (do_one_initcall+0x11c/0x1dc) [<>] (do_one_initcall) from [<>] (kernel_init_freeable+0x10c/0x1d4) [<>] (kernel_init_freeable) from [<>] (kernel_init+0x10/0xec) [<>] (kernel_init) from [<>] (ret_from_fork+0x14/0x24) Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
1015 lines
28 KiB
C
1015 lines
28 KiB
C
/*
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* NXP LPC32XX NAND SLC driver
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*
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* Authors:
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* Kevin Wells <kevin.wells@nxp.com>
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* Roland Stigge <stigge@antcom.de>
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*
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* Copyright © 2011 NXP Semiconductors
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* Copyright © 2012 Roland Stigge
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/gpio.h>
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#include <linux/of.h>
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#include <linux/of_mtd.h>
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#include <linux/of_gpio.h>
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#include <linux/mtd/lpc32xx_slc.h>
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#define LPC32XX_MODNAME "lpc32xx-nand"
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/**********************************************************************
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* SLC NAND controller register offsets
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**********************************************************************/
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#define SLC_DATA(x) (x + 0x000)
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#define SLC_ADDR(x) (x + 0x004)
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#define SLC_CMD(x) (x + 0x008)
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#define SLC_STOP(x) (x + 0x00C)
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#define SLC_CTRL(x) (x + 0x010)
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#define SLC_CFG(x) (x + 0x014)
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#define SLC_STAT(x) (x + 0x018)
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#define SLC_INT_STAT(x) (x + 0x01C)
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#define SLC_IEN(x) (x + 0x020)
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#define SLC_ISR(x) (x + 0x024)
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#define SLC_ICR(x) (x + 0x028)
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#define SLC_TAC(x) (x + 0x02C)
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#define SLC_TC(x) (x + 0x030)
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#define SLC_ECC(x) (x + 0x034)
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#define SLC_DMA_DATA(x) (x + 0x038)
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/**********************************************************************
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* slc_ctrl register definitions
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**********************************************************************/
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#define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */
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#define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
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#define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */
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/**********************************************************************
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* slc_cfg register definitions
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**********************************************************************/
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#define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */
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#define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
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#define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
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#define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */
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#define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
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#define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */
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/**********************************************************************
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* slc_stat register definitions
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**********************************************************************/
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#define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
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#define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */
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#define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */
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/**********************************************************************
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* slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions
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**********************************************************************/
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#define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */
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#define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */
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/**********************************************************************
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* slc_tac register definitions
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**********************************************************************/
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/* Computation of clock cycles on basis of controller and device clock rates */
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#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
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/* Clock setting for RDY write sample wait time in 2*n clocks */
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#define SLCTAC_WDR(n) (((n) & 0xF) << 28)
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/* Write pulse width in clock cycles, 1 to 16 clocks */
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#define SLCTAC_WWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 24))
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/* Write hold time of control and data signals, 1 to 16 clocks */
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#define SLCTAC_WHOLD(c, n) (SLCTAC_CLOCKS(c, n, 20))
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/* Write setup time of control and data signals, 1 to 16 clocks */
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#define SLCTAC_WSETUP(c, n) (SLCTAC_CLOCKS(c, n, 16))
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/* Clock setting for RDY read sample wait time in 2*n clocks */
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#define SLCTAC_RDR(n) (((n) & 0xF) << 12)
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/* Read pulse width in clock cycles, 1 to 16 clocks */
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#define SLCTAC_RWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 8))
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/* Read hold time of control and data signals, 1 to 16 clocks */
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#define SLCTAC_RHOLD(c, n) (SLCTAC_CLOCKS(c, n, 4))
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/* Read setup time of control and data signals, 1 to 16 clocks */
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#define SLCTAC_RSETUP(c, n) (SLCTAC_CLOCKS(c, n, 0))
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/**********************************************************************
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* slc_ecc register definitions
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**********************************************************************/
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/* ECC line party fetch macro */
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#define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF)
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#define SLCECC_TO_COLPAR(n) ((n) & 0x3F)
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/*
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* DMA requires storage space for the DMA local buffer and the hardware ECC
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* storage area. The DMA local buffer is only used if DMA mapping fails
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* during runtime.
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*/
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#define LPC32XX_DMA_DATA_SIZE 4096
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#define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4)
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/* Number of bytes used for ECC stored in NAND per 256 bytes */
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#define LPC32XX_SLC_DEV_ECC_BYTES 3
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/*
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* If the NAND base clock frequency can't be fetched, this frequency will be
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* used instead as the base. This rate is used to setup the timing registers
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* used for NAND accesses.
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*/
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#define LPC32XX_DEF_BUS_RATE 133250000
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/* Milliseconds for DMA FIFO timeout (unlikely anyway) */
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#define LPC32XX_DMA_TIMEOUT 100
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/*
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* NAND ECC Layout for small page NAND devices
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* Note: For large and huge page devices, the default layouts are used
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*/
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static struct nand_ecclayout lpc32xx_nand_oob_16 = {
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.eccbytes = 6,
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.eccpos = {10, 11, 12, 13, 14, 15},
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.oobfree = {
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{ .offset = 0, .length = 4 },
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{ .offset = 6, .length = 4 },
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},
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};
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static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
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static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
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/*
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* Small page FLASH BBT descriptors, marker at offset 0, version at offset 6
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* Note: Large page devices used the default layout
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*/
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static struct nand_bbt_descr bbt_smallpage_main_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
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| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
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.offs = 0,
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.len = 4,
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.veroffs = 6,
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.maxblocks = 4,
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.pattern = bbt_pattern
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};
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static struct nand_bbt_descr bbt_smallpage_mirror_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
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| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
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.offs = 0,
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.len = 4,
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.veroffs = 6,
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.maxblocks = 4,
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.pattern = mirror_pattern
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};
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/*
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* NAND platform configuration structure
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*/
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struct lpc32xx_nand_cfg_slc {
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uint32_t wdr_clks;
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uint32_t wwidth;
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uint32_t whold;
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uint32_t wsetup;
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uint32_t rdr_clks;
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uint32_t rwidth;
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uint32_t rhold;
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uint32_t rsetup;
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bool use_bbt;
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int wp_gpio;
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struct mtd_partition *parts;
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unsigned num_parts;
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};
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struct lpc32xx_nand_host {
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struct nand_chip nand_chip;
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struct lpc32xx_slc_platform_data *pdata;
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struct clk *clk;
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struct mtd_info mtd;
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void __iomem *io_base;
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struct lpc32xx_nand_cfg_slc *ncfg;
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struct completion comp;
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struct dma_chan *dma_chan;
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uint32_t dma_buf_len;
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struct dma_slave_config dma_slave_config;
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struct scatterlist sgl;
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/*
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* DMA and CPU addresses of ECC work area and data buffer
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*/
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uint32_t *ecc_buf;
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uint8_t *data_buf;
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dma_addr_t io_base_dma;
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};
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static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
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{
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uint32_t clkrate, tmp;
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/* Reset SLC controller */
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writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
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udelay(1000);
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/* Basic setup */
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writel(0, SLC_CFG(host->io_base));
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writel(0, SLC_IEN(host->io_base));
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writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
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SLC_ICR(host->io_base));
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/* Get base clock for SLC block */
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clkrate = clk_get_rate(host->clk);
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if (clkrate == 0)
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clkrate = LPC32XX_DEF_BUS_RATE;
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/* Compute clock setup values */
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tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
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SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) |
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SLCTAC_WHOLD(clkrate, host->ncfg->whold) |
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SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) |
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SLCTAC_RDR(host->ncfg->rdr_clks) |
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SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) |
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SLCTAC_RHOLD(clkrate, host->ncfg->rhold) |
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SLCTAC_RSETUP(clkrate, host->ncfg->rsetup);
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writel(tmp, SLC_TAC(host->io_base));
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}
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/*
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* Hardware specific access to control lines
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*/
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static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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uint32_t tmp;
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struct nand_chip *chip = mtd->priv;
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struct lpc32xx_nand_host *host = chip->priv;
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/* Does CE state need to be changed? */
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tmp = readl(SLC_CFG(host->io_base));
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if (ctrl & NAND_NCE)
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tmp |= SLCCFG_CE_LOW;
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else
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tmp &= ~SLCCFG_CE_LOW;
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writel(tmp, SLC_CFG(host->io_base));
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if (cmd != NAND_CMD_NONE) {
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if (ctrl & NAND_CLE)
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writel(cmd, SLC_CMD(host->io_base));
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else
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writel(cmd, SLC_ADDR(host->io_base));
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}
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}
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/*
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* Read the Device Ready pin
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*/
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static int lpc32xx_nand_device_ready(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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struct lpc32xx_nand_host *host = chip->priv;
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int rdy = 0;
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if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
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rdy = 1;
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return rdy;
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}
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/*
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* Enable NAND write protect
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*/
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static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
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{
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if (gpio_is_valid(host->ncfg->wp_gpio))
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gpio_set_value(host->ncfg->wp_gpio, 0);
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}
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/*
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* Disable NAND write protect
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*/
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static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
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{
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if (gpio_is_valid(host->ncfg->wp_gpio))
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gpio_set_value(host->ncfg->wp_gpio, 1);
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}
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/*
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* Prepares SLC for transfers with H/W ECC enabled
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*/
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static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode)
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{
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/* Hardware ECC is enabled automatically in hardware as needed */
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}
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/*
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* Calculates the ECC for the data
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*/
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static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd,
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const unsigned char *buf,
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unsigned char *code)
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{
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/*
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* ECC is calculated automatically in hardware during syndrome read
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* and write operations, so it doesn't need to be calculated here.
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*/
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return 0;
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}
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/*
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* Read a single byte from NAND device
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*/
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static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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struct lpc32xx_nand_host *host = chip->priv;
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return (uint8_t)readl(SLC_DATA(host->io_base));
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}
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/*
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* Simple device read without ECC
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*/
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static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct nand_chip *chip = mtd->priv;
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struct lpc32xx_nand_host *host = chip->priv;
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/* Direct device read with no ECC */
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while (len-- > 0)
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*buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
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}
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/*
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* Simple device write without ECC
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*/
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static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd->priv;
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struct lpc32xx_nand_host *host = chip->priv;
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/* Direct device write with no ECC */
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while (len-- > 0)
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writel((uint32_t)*buf++, SLC_DATA(host->io_base));
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}
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/*
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* Read the OOB data from the device without ECC using FIFO method
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*/
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static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd,
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struct nand_chip *chip, int page)
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{
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chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
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chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
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return 0;
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}
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/*
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* Write the OOB data to the device without ECC using FIFO method
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*/
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static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd,
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struct nand_chip *chip, int page)
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{
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int status;
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chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
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chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
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/* Send command to program the OOB data */
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chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
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status = chip->waitfunc(mtd, chip);
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return status & NAND_STATUS_FAIL ? -EIO : 0;
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}
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/*
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* Fills in the ECC fields in the OOB buffer with the hardware generated ECC
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*/
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static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)
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{
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int i;
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for (i = 0; i < (count * 3); i += 3) {
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uint32_t ce = ecc[i / 3];
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ce = ~(ce << 2) & 0xFFFFFF;
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spare[i + 2] = (uint8_t)(ce & 0xFF);
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ce >>= 8;
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spare[i + 1] = (uint8_t)(ce & 0xFF);
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ce >>= 8;
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spare[i] = (uint8_t)(ce & 0xFF);
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}
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}
|
|
|
|
static void lpc32xx_dma_complete_func(void *completion)
|
|
{
|
|
complete(completion);
|
|
}
|
|
|
|
static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
|
|
void *mem, int len, enum dma_transfer_direction dir)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct lpc32xx_nand_host *host = chip->priv;
|
|
struct dma_async_tx_descriptor *desc;
|
|
int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
|
|
int res;
|
|
|
|
host->dma_slave_config.direction = dir;
|
|
host->dma_slave_config.src_addr = dma;
|
|
host->dma_slave_config.dst_addr = dma;
|
|
host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
host->dma_slave_config.src_maxburst = 4;
|
|
host->dma_slave_config.dst_maxburst = 4;
|
|
/* DMA controller does flow control: */
|
|
host->dma_slave_config.device_fc = false;
|
|
if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
|
|
dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
sg_init_one(&host->sgl, mem, len);
|
|
|
|
res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
|
|
DMA_BIDIRECTIONAL);
|
|
if (res != 1) {
|
|
dev_err(mtd->dev.parent, "Failed to map sg list\n");
|
|
return -ENXIO;
|
|
}
|
|
desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
|
|
flags);
|
|
if (!desc) {
|
|
dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
|
|
goto out1;
|
|
}
|
|
|
|
init_completion(&host->comp);
|
|
desc->callback = lpc32xx_dma_complete_func;
|
|
desc->callback_param = &host->comp;
|
|
|
|
dmaengine_submit(desc);
|
|
dma_async_issue_pending(host->dma_chan);
|
|
|
|
wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
|
|
|
|
dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
return 0;
|
|
out1:
|
|
dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
|
|
DMA_BIDIRECTIONAL);
|
|
return -ENXIO;
|
|
}
|
|
|
|
/*
|
|
* DMA read/write transfers with ECC support
|
|
*/
|
|
static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages,
|
|
int read)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct lpc32xx_nand_host *host = chip->priv;
|
|
int i, status = 0;
|
|
unsigned long timeout;
|
|
int res;
|
|
enum dma_transfer_direction dir =
|
|
read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
|
|
uint8_t *dma_buf;
|
|
bool dma_mapped;
|
|
|
|
if ((void *)buf <= high_memory) {
|
|
dma_buf = buf;
|
|
dma_mapped = true;
|
|
} else {
|
|
dma_buf = host->data_buf;
|
|
dma_mapped = false;
|
|
if (!read)
|
|
memcpy(host->data_buf, buf, mtd->writesize);
|
|
}
|
|
|
|
if (read) {
|
|
writel(readl(SLC_CFG(host->io_base)) |
|
|
SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
|
|
SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
|
|
} else {
|
|
writel((readl(SLC_CFG(host->io_base)) |
|
|
SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) &
|
|
~SLCCFG_DMA_DIR,
|
|
SLC_CFG(host->io_base));
|
|
}
|
|
|
|
/* Clear initial ECC */
|
|
writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
|
|
|
|
/* Transfer size is data area only */
|
|
writel(mtd->writesize, SLC_TC(host->io_base));
|
|
|
|
/* Start transfer in the NAND controller */
|
|
writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
|
|
SLC_CTRL(host->io_base));
|
|
|
|
for (i = 0; i < chip->ecc.steps; i++) {
|
|
/* Data */
|
|
res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
|
|
dma_buf + i * chip->ecc.size,
|
|
mtd->writesize / chip->ecc.steps, dir);
|
|
if (res)
|
|
return res;
|
|
|
|
/* Always _read_ ECC */
|
|
if (i == chip->ecc.steps - 1)
|
|
break;
|
|
if (!read) /* ECC availability delayed on write */
|
|
udelay(10);
|
|
res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
|
|
&host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
|
|
if (res)
|
|
return res;
|
|
}
|
|
|
|
/*
|
|
* According to NXP, the DMA can be finished here, but the NAND
|
|
* controller may still have buffered data. After porting to using the
|
|
* dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty)
|
|
* appears to be always true, according to tests. Keeping the check for
|
|
* safety reasons for now.
|
|
*/
|
|
if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
|
|
dev_warn(mtd->dev.parent, "FIFO not empty!\n");
|
|
timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT);
|
|
while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
|
|
time_before(jiffies, timeout))
|
|
cpu_relax();
|
|
if (!time_before(jiffies, timeout)) {
|
|
dev_err(mtd->dev.parent, "FIFO held data too long\n");
|
|
status = -EIO;
|
|
}
|
|
}
|
|
|
|
/* Read last calculated ECC value */
|
|
if (!read)
|
|
udelay(10);
|
|
host->ecc_buf[chip->ecc.steps - 1] =
|
|
readl(SLC_ECC(host->io_base));
|
|
|
|
/* Flush DMA */
|
|
dmaengine_terminate_all(host->dma_chan);
|
|
|
|
if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
|
|
readl(SLC_TC(host->io_base))) {
|
|
/* Something is left in the FIFO, something is wrong */
|
|
dev_err(mtd->dev.parent, "DMA FIFO failure\n");
|
|
status = -EIO;
|
|
}
|
|
|
|
/* Stop DMA & HW ECC */
|
|
writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
|
|
SLC_CTRL(host->io_base));
|
|
writel(readl(SLC_CFG(host->io_base)) &
|
|
~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
|
|
SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
|
|
|
|
if (!dma_mapped && read)
|
|
memcpy(buf, host->data_buf, mtd->writesize);
|
|
|
|
return status;
|
|
}
|
|
|
|
/*
|
|
* Read the data and OOB data from the device, use ECC correction with the
|
|
* data, disable ECC for the OOB data
|
|
*/
|
|
static int lpc32xx_nand_read_page_syndrome(struct mtd_info *mtd,
|
|
struct nand_chip *chip, uint8_t *buf,
|
|
int oob_required, int page)
|
|
{
|
|
struct lpc32xx_nand_host *host = chip->priv;
|
|
int stat, i, status;
|
|
uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE];
|
|
|
|
/* Issue read command */
|
|
chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
|
|
|
|
/* Read data and oob, calculate ECC */
|
|
status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
|
|
|
|
/* Get OOB data */
|
|
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
/* Convert to stored ECC format */
|
|
lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
|
|
|
|
/* Pointer to ECC data retrieved from NAND spare area */
|
|
oobecc = chip->oob_poi + chip->ecc.layout->eccpos[0];
|
|
|
|
for (i = 0; i < chip->ecc.steps; i++) {
|
|
stat = chip->ecc.correct(mtd, buf, oobecc,
|
|
&tmpecc[i * chip->ecc.bytes]);
|
|
if (stat < 0)
|
|
mtd->ecc_stats.failed++;
|
|
else
|
|
mtd->ecc_stats.corrected += stat;
|
|
|
|
buf += chip->ecc.size;
|
|
oobecc += chip->ecc.bytes;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/*
|
|
* Read the data and OOB data from the device, no ECC correction with the
|
|
* data or OOB data
|
|
*/
|
|
static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd,
|
|
struct nand_chip *chip,
|
|
uint8_t *buf, int oob_required,
|
|
int page)
|
|
{
|
|
/* Issue read command */
|
|
chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
|
|
|
|
/* Raw reads can just use the FIFO interface */
|
|
chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
|
|
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Write the data and OOB data to the device, use ECC with the data,
|
|
* disable ECC for the OOB data
|
|
*/
|
|
static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
|
|
struct nand_chip *chip,
|
|
const uint8_t *buf,
|
|
int oob_required, int page)
|
|
{
|
|
struct lpc32xx_nand_host *host = chip->priv;
|
|
uint8_t *pb = chip->oob_poi + chip->ecc.layout->eccpos[0];
|
|
int error;
|
|
|
|
/* Write data, calculate ECC on outbound data */
|
|
error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
|
|
if (error)
|
|
return error;
|
|
|
|
/*
|
|
* The calculated ECC needs some manual work done to it before
|
|
* committing it to NAND. Process the calculated ECC and place
|
|
* the resultant values directly into the OOB buffer. */
|
|
lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
|
|
|
|
/* Write ECC data to device */
|
|
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Write the data and OOB data to the device, no ECC correction with the
|
|
* data or OOB data
|
|
*/
|
|
static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd,
|
|
struct nand_chip *chip,
|
|
const uint8_t *buf,
|
|
int oob_required, int page)
|
|
{
|
|
/* Raw writes can just use the FIFO interface */
|
|
chip->write_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
|
|
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
return 0;
|
|
}
|
|
|
|
static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
|
|
{
|
|
struct mtd_info *mtd = &host->mtd;
|
|
dma_cap_mask_t mask;
|
|
|
|
if (!host->pdata || !host->pdata->dma_filter) {
|
|
dev_err(mtd->dev.parent, "no DMA platform data\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
dma_cap_zero(mask);
|
|
dma_cap_set(DMA_SLAVE, mask);
|
|
host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
|
|
"nand-slc");
|
|
if (!host->dma_chan) {
|
|
dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
|
|
{
|
|
struct lpc32xx_nand_cfg_slc *ncfg;
|
|
struct device_node *np = dev->of_node;
|
|
|
|
ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
|
|
if (!ncfg)
|
|
return NULL;
|
|
|
|
of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks);
|
|
of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth);
|
|
of_property_read_u32(np, "nxp,whold", &ncfg->whold);
|
|
of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup);
|
|
of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks);
|
|
of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth);
|
|
of_property_read_u32(np, "nxp,rhold", &ncfg->rhold);
|
|
of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup);
|
|
|
|
if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold ||
|
|
!ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth ||
|
|
!ncfg->rhold || !ncfg->rsetup) {
|
|
dev_err(dev, "chip parameters not specified correctly\n");
|
|
return NULL;
|
|
}
|
|
|
|
ncfg->use_bbt = of_get_nand_on_flash_bbt(np);
|
|
ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
|
|
|
|
return ncfg;
|
|
}
|
|
|
|
/*
|
|
* Probe for NAND controller
|
|
*/
|
|
static int lpc32xx_nand_probe(struct platform_device *pdev)
|
|
{
|
|
struct lpc32xx_nand_host *host;
|
|
struct mtd_info *mtd;
|
|
struct nand_chip *chip;
|
|
struct resource *rc;
|
|
struct mtd_part_parser_data ppdata = {};
|
|
int res;
|
|
|
|
rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (rc == NULL) {
|
|
dev_err(&pdev->dev, "No memory resource found for device\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
/* Allocate memory for the device structure (and zero it) */
|
|
host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
|
|
if (!host)
|
|
return -ENOMEM;
|
|
host->io_base_dma = rc->start;
|
|
|
|
host->io_base = devm_ioremap_resource(&pdev->dev, rc);
|
|
if (IS_ERR(host->io_base))
|
|
return PTR_ERR(host->io_base);
|
|
|
|
if (pdev->dev.of_node)
|
|
host->ncfg = lpc32xx_parse_dt(&pdev->dev);
|
|
if (!host->ncfg) {
|
|
dev_err(&pdev->dev,
|
|
"Missing or bad NAND config from device tree\n");
|
|
return -ENOENT;
|
|
}
|
|
if (host->ncfg->wp_gpio == -EPROBE_DEFER)
|
|
return -EPROBE_DEFER;
|
|
if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev,
|
|
host->ncfg->wp_gpio, "NAND WP")) {
|
|
dev_err(&pdev->dev, "GPIO not available\n");
|
|
return -EBUSY;
|
|
}
|
|
lpc32xx_wp_disable(host);
|
|
|
|
host->pdata = dev_get_platdata(&pdev->dev);
|
|
|
|
mtd = &host->mtd;
|
|
chip = &host->nand_chip;
|
|
chip->priv = host;
|
|
mtd->priv = chip;
|
|
mtd->owner = THIS_MODULE;
|
|
mtd->dev.parent = &pdev->dev;
|
|
|
|
/* Get NAND clock */
|
|
host->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(host->clk)) {
|
|
dev_err(&pdev->dev, "Clock failure\n");
|
|
res = -ENOENT;
|
|
goto err_exit1;
|
|
}
|
|
clk_prepare_enable(host->clk);
|
|
|
|
/* Set NAND IO addresses and command/ready functions */
|
|
chip->IO_ADDR_R = SLC_DATA(host->io_base);
|
|
chip->IO_ADDR_W = SLC_DATA(host->io_base);
|
|
chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
|
|
chip->dev_ready = lpc32xx_nand_device_ready;
|
|
chip->chip_delay = 20; /* 20us command delay time */
|
|
|
|
/* Init NAND controller */
|
|
lpc32xx_nand_setup(host);
|
|
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
/* NAND callbacks for LPC32xx SLC hardware */
|
|
chip->ecc.mode = NAND_ECC_HW_SYNDROME;
|
|
chip->read_byte = lpc32xx_nand_read_byte;
|
|
chip->read_buf = lpc32xx_nand_read_buf;
|
|
chip->write_buf = lpc32xx_nand_write_buf;
|
|
chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
|
|
chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
|
|
chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
|
|
chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
|
|
chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
|
|
chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
|
|
chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
|
|
chip->ecc.correct = nand_correct_data;
|
|
chip->ecc.strength = 1;
|
|
chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
|
|
|
|
/*
|
|
* Allocate a large enough buffer for a single huge page plus
|
|
* extra space for the spare area and ECC storage area
|
|
*/
|
|
host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
|
|
host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
|
|
GFP_KERNEL);
|
|
if (host->data_buf == NULL) {
|
|
res = -ENOMEM;
|
|
goto err_exit2;
|
|
}
|
|
|
|
res = lpc32xx_nand_dma_setup(host);
|
|
if (res) {
|
|
res = -EIO;
|
|
goto err_exit2;
|
|
}
|
|
|
|
/* Find NAND device */
|
|
if (nand_scan_ident(mtd, 1, NULL)) {
|
|
res = -ENXIO;
|
|
goto err_exit3;
|
|
}
|
|
|
|
/* OOB and ECC CPU and DMA work areas */
|
|
host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
|
|
|
|
/*
|
|
* Small page FLASH has a unique OOB layout, but large and huge
|
|
* page FLASH use the standard layout. Small page FLASH uses a
|
|
* custom BBT marker layout.
|
|
*/
|
|
if (mtd->writesize <= 512)
|
|
chip->ecc.layout = &lpc32xx_nand_oob_16;
|
|
|
|
/* These sizes remain the same regardless of page size */
|
|
chip->ecc.size = 256;
|
|
chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
|
|
chip->ecc.prepad = chip->ecc.postpad = 0;
|
|
|
|
/* Avoid extra scan if using BBT, setup BBT support */
|
|
if (host->ncfg->use_bbt) {
|
|
chip->bbt_options |= NAND_BBT_USE_FLASH;
|
|
|
|
/*
|
|
* Use a custom BBT marker setup for small page FLASH that
|
|
* won't interfere with the ECC layout. Large and huge page
|
|
* FLASH use the standard layout.
|
|
*/
|
|
if (mtd->writesize <= 512) {
|
|
chip->bbt_td = &bbt_smallpage_main_descr;
|
|
chip->bbt_md = &bbt_smallpage_mirror_descr;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Fills out all the uninitialized function pointers with the defaults
|
|
*/
|
|
if (nand_scan_tail(mtd)) {
|
|
res = -ENXIO;
|
|
goto err_exit3;
|
|
}
|
|
|
|
mtd->name = "nxp_lpc3220_slc";
|
|
ppdata.of_node = pdev->dev.of_node;
|
|
res = mtd_device_parse_register(mtd, NULL, &ppdata, host->ncfg->parts,
|
|
host->ncfg->num_parts);
|
|
if (!res)
|
|
return res;
|
|
|
|
nand_release(mtd);
|
|
|
|
err_exit3:
|
|
dma_release_channel(host->dma_chan);
|
|
err_exit2:
|
|
clk_disable_unprepare(host->clk);
|
|
err_exit1:
|
|
lpc32xx_wp_enable(host);
|
|
|
|
return res;
|
|
}
|
|
|
|
/*
|
|
* Remove NAND device.
|
|
*/
|
|
static int lpc32xx_nand_remove(struct platform_device *pdev)
|
|
{
|
|
uint32_t tmp;
|
|
struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
|
|
struct mtd_info *mtd = &host->mtd;
|
|
|
|
nand_release(mtd);
|
|
dma_release_channel(host->dma_chan);
|
|
|
|
/* Force CE high */
|
|
tmp = readl(SLC_CTRL(host->io_base));
|
|
tmp &= ~SLCCFG_CE_LOW;
|
|
writel(tmp, SLC_CTRL(host->io_base));
|
|
|
|
clk_disable_unprepare(host->clk);
|
|
lpc32xx_wp_enable(host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int lpc32xx_nand_resume(struct platform_device *pdev)
|
|
{
|
|
struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
|
|
|
|
/* Re-enable NAND clock */
|
|
clk_prepare_enable(host->clk);
|
|
|
|
/* Fresh init of NAND controller */
|
|
lpc32xx_nand_setup(host);
|
|
|
|
/* Disable write protect */
|
|
lpc32xx_wp_disable(host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
|
|
{
|
|
uint32_t tmp;
|
|
struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
|
|
|
|
/* Force CE high */
|
|
tmp = readl(SLC_CTRL(host->io_base));
|
|
tmp &= ~SLCCFG_CE_LOW;
|
|
writel(tmp, SLC_CTRL(host->io_base));
|
|
|
|
/* Enable write protect for safety */
|
|
lpc32xx_wp_enable(host);
|
|
|
|
/* Disable clock */
|
|
clk_disable_unprepare(host->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define lpc32xx_nand_resume NULL
|
|
#define lpc32xx_nand_suspend NULL
|
|
#endif
|
|
|
|
static const struct of_device_id lpc32xx_nand_match[] = {
|
|
{ .compatible = "nxp,lpc3220-slc" },
|
|
{ /* sentinel */ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
|
|
|
|
static struct platform_driver lpc32xx_nand_driver = {
|
|
.probe = lpc32xx_nand_probe,
|
|
.remove = lpc32xx_nand_remove,
|
|
.resume = lpc32xx_nand_resume,
|
|
.suspend = lpc32xx_nand_suspend,
|
|
.driver = {
|
|
.name = LPC32XX_MODNAME,
|
|
.of_match_table = lpc32xx_nand_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(lpc32xx_nand_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
|
|
MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
|
|
MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");
|