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![Johan Hovold](/assets/img/avatar_default.png)
Make sure only to copy any actual data rather than the whole buffer, when releasing the temporary buffer used for unaligned non-isochronous transfers. Compile-tested only. Signed-off-by: Johan Hovold <johan@kernel.org> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
627 lines
16 KiB
C
627 lines
16 KiB
C
/*
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* EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
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*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (C) 2009 - 2013 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/usb/ehci_def.h>
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#include <linux/usb/tegra_usb_phy.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/otg.h>
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#include "ehci.h"
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#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
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#define TEGRA_USB_DMA_ALIGN 32
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#define DRIVER_DESC "Tegra EHCI driver"
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#define DRV_NAME "tegra-ehci"
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static struct hc_driver __read_mostly tegra_ehci_hc_driver;
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static bool usb1_reset_attempted;
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struct tegra_ehci_soc_config {
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bool has_hostpc;
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};
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struct tegra_ehci_hcd {
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struct tegra_usb_phy *phy;
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struct clk *clk;
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struct reset_control *rst;
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int port_resuming;
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bool needs_double_reset;
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enum tegra_usb_phy_port_speed port_speed;
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};
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/*
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* The 1st USB controller contains some UTMI pad registers that are global for
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* all the controllers on the chip. Those registers are also cleared when
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* reset is asserted to the 1st controller. This means that the 1st controller
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* can only be reset when no other controlled has finished probing. So we'll
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* reset the 1st controller before doing any other setup on any of the
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* controllers, and then never again.
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*
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* Since this is a PHY issue, the Tegra PHY driver should probably be doing
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* the resetting of the USB controllers. But to keep compatibility with old
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* device trees that don't have reset phandles in the PHYs, do it here.
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* Those old DTs will be vulnerable to total USB breakage if the 1st EHCI
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* device isn't the first one to finish probing, so warn them.
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*/
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static int tegra_reset_usb_controller(struct platform_device *pdev)
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{
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struct device_node *phy_np;
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struct usb_hcd *hcd = platform_get_drvdata(pdev);
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struct tegra_ehci_hcd *tegra =
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(struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
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phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
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if (!phy_np)
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return -ENOENT;
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if (!usb1_reset_attempted) {
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struct reset_control *usb1_reset;
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usb1_reset = of_reset_control_get(phy_np, "usb");
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if (IS_ERR(usb1_reset)) {
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dev_warn(&pdev->dev,
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"can't get utmi-pads reset from the PHY\n");
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dev_warn(&pdev->dev,
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"continuing, but please update your DT\n");
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} else {
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reset_control_assert(usb1_reset);
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udelay(1);
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reset_control_deassert(usb1_reset);
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}
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reset_control_put(usb1_reset);
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usb1_reset_attempted = true;
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}
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if (!of_property_read_bool(phy_np, "nvidia,has-utmi-pad-registers")) {
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reset_control_assert(tegra->rst);
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udelay(1);
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reset_control_deassert(tegra->rst);
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}
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of_node_put(phy_np);
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return 0;
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}
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static int tegra_ehci_internal_port_reset(
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struct ehci_hcd *ehci,
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u32 __iomem *portsc_reg
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)
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{
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u32 temp;
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unsigned long flags;
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int retval = 0;
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int i, tries;
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u32 saved_usbintr;
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spin_lock_irqsave(&ehci->lock, flags);
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saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
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/* disable USB interrupt */
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ehci_writel(ehci, 0, &ehci->regs->intr_enable);
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spin_unlock_irqrestore(&ehci->lock, flags);
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/*
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* Here we have to do Port Reset at most twice for
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* Port Enable bit to be set.
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*/
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for (i = 0; i < 2; i++) {
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temp = ehci_readl(ehci, portsc_reg);
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temp |= PORT_RESET;
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ehci_writel(ehci, temp, portsc_reg);
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mdelay(10);
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temp &= ~PORT_RESET;
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ehci_writel(ehci, temp, portsc_reg);
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mdelay(1);
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tries = 100;
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do {
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mdelay(1);
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/*
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* Up to this point, Port Enable bit is
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* expected to be set after 2 ms waiting.
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* USB1 usually takes extra 45 ms, for safety,
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* we take 100 ms as timeout.
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*/
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temp = ehci_readl(ehci, portsc_reg);
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} while (!(temp & PORT_PE) && tries--);
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if (temp & PORT_PE)
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break;
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}
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if (i == 2)
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retval = -ETIMEDOUT;
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/*
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* Clear Connect Status Change bit if it's set.
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* We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
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*/
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if (temp & PORT_CSC)
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ehci_writel(ehci, PORT_CSC, portsc_reg);
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/*
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* Write to clear any interrupt status bits that might be set
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* during port reset.
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*/
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temp = ehci_readl(ehci, &ehci->regs->status);
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ehci_writel(ehci, temp, &ehci->regs->status);
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/* restore original interrupt enable bits */
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ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
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return retval;
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}
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static int tegra_ehci_hub_control(
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struct usb_hcd *hcd,
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u16 typeReq,
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u16 wValue,
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u16 wIndex,
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char *buf,
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u16 wLength
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)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
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u32 __iomem *status_reg;
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u32 temp;
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unsigned long flags;
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int retval = 0;
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status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
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spin_lock_irqsave(&ehci->lock, flags);
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if (typeReq == GetPortStatus) {
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temp = ehci_readl(ehci, status_reg);
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if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
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/* Resume completed, re-enable disconnect detection */
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tegra->port_resuming = 0;
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tegra_usb_phy_postresume(hcd->usb_phy);
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}
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}
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else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
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temp = ehci_readl(ehci, status_reg);
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if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
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retval = -EPIPE;
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goto done;
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}
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temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
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temp |= PORT_WKDISC_E | PORT_WKOC_E;
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ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
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/*
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* If a transaction is in progress, there may be a delay in
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* suspending the port. Poll until the port is suspended.
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*/
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if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
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PORT_SUSPEND, 5000))
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pr_err("%s: timeout waiting for SUSPEND\n", __func__);
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set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
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goto done;
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}
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/* For USB1 port we need to issue Port Reset twice internally */
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if (tegra->needs_double_reset &&
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(typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
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spin_unlock_irqrestore(&ehci->lock, flags);
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return tegra_ehci_internal_port_reset(ehci, status_reg);
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}
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/*
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* Tegra host controller will time the resume operation to clear the bit
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* when the port control state switches to HS or FS Idle. This behavior
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* is different from EHCI where the host controller driver is required
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* to set this bit to a zero after the resume duration is timed in the
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* driver.
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*/
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else if (typeReq == ClearPortFeature &&
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wValue == USB_PORT_FEAT_SUSPEND) {
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temp = ehci_readl(ehci, status_reg);
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if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
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retval = -EPIPE;
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goto done;
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}
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if (!(temp & PORT_SUSPEND))
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goto done;
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/* Disable disconnect detection during port resume */
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tegra_usb_phy_preresume(hcd->usb_phy);
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ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
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temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
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/* start resume signalling */
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ehci_writel(ehci, temp | PORT_RESUME, status_reg);
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set_bit(wIndex-1, &ehci->resuming_ports);
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spin_unlock_irqrestore(&ehci->lock, flags);
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msleep(20);
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spin_lock_irqsave(&ehci->lock, flags);
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/* Poll until the controller clears RESUME and SUSPEND */
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if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
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pr_err("%s: timeout waiting for RESUME\n", __func__);
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if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
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pr_err("%s: timeout waiting for SUSPEND\n", __func__);
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ehci->reset_done[wIndex-1] = 0;
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clear_bit(wIndex-1, &ehci->resuming_ports);
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tegra->port_resuming = 1;
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goto done;
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}
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spin_unlock_irqrestore(&ehci->lock, flags);
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/* Handle the hub control events here */
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return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
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done:
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spin_unlock_irqrestore(&ehci->lock, flags);
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return retval;
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}
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struct dma_aligned_buffer {
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void *kmalloc_ptr;
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void *old_xfer_buffer;
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u8 data[0];
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};
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static void free_dma_aligned_buffer(struct urb *urb)
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{
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struct dma_aligned_buffer *temp;
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size_t length;
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if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
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return;
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temp = container_of(urb->transfer_buffer,
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struct dma_aligned_buffer, data);
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if (usb_urb_dir_in(urb)) {
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if (usb_pipeisoc(urb->pipe))
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length = urb->transfer_buffer_length;
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else
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length = urb->actual_length;
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memcpy(temp->old_xfer_buffer, temp->data, length);
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}
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urb->transfer_buffer = temp->old_xfer_buffer;
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kfree(temp->kmalloc_ptr);
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urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
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}
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static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
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{
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struct dma_aligned_buffer *temp, *kmalloc_ptr;
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size_t kmalloc_size;
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if (urb->num_sgs || urb->sg ||
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urb->transfer_buffer_length == 0 ||
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!((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
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return 0;
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/* Allocate a buffer with enough padding for alignment */
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kmalloc_size = urb->transfer_buffer_length +
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sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
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kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
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if (!kmalloc_ptr)
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return -ENOMEM;
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/* Position our struct dma_aligned_buffer such that data is aligned */
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temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
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temp->kmalloc_ptr = kmalloc_ptr;
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temp->old_xfer_buffer = urb->transfer_buffer;
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if (usb_urb_dir_out(urb))
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memcpy(temp->data, urb->transfer_buffer,
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urb->transfer_buffer_length);
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urb->transfer_buffer = temp->data;
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urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
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return 0;
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}
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static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
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gfp_t mem_flags)
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{
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int ret;
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ret = alloc_dma_aligned_buffer(urb, mem_flags);
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if (ret)
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return ret;
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ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
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if (ret)
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free_dma_aligned_buffer(urb);
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return ret;
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}
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static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
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{
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usb_hcd_unmap_urb_for_dma(hcd, urb);
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free_dma_aligned_buffer(urb);
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}
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static const struct tegra_ehci_soc_config tegra30_soc_config = {
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.has_hostpc = true,
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};
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static const struct tegra_ehci_soc_config tegra20_soc_config = {
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.has_hostpc = false,
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};
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static const struct of_device_id tegra_ehci_of_match[] = {
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{ .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
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{ .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
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{ },
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};
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static int tegra_ehci_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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const struct tegra_ehci_soc_config *soc_config;
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struct resource *res;
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struct usb_hcd *hcd;
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struct ehci_hcd *ehci;
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struct tegra_ehci_hcd *tegra;
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int err = 0;
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int irq;
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struct usb_phy *u_phy;
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match = of_match_device(tegra_ehci_of_match, &pdev->dev);
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if (!match) {
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dev_err(&pdev->dev, "Error: No device match found\n");
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return -ENODEV;
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}
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soc_config = match->data;
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/* Right now device-tree probed devices don't get dma_mask set.
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* Since shared usb code relies on it, set it here for now.
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* Once we have dma capability bindings this can go away.
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*/
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err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
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if (err)
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return err;
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hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
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dev_name(&pdev->dev));
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if (!hcd) {
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dev_err(&pdev->dev, "Unable to create HCD\n");
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return -ENOMEM;
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}
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platform_set_drvdata(pdev, hcd);
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ehci = hcd_to_ehci(hcd);
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tegra = (struct tegra_ehci_hcd *)ehci->priv;
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hcd->has_tt = 1;
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tegra->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(tegra->clk)) {
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dev_err(&pdev->dev, "Can't get ehci clock\n");
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err = PTR_ERR(tegra->clk);
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goto cleanup_hcd_create;
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}
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tegra->rst = devm_reset_control_get(&pdev->dev, "usb");
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if (IS_ERR(tegra->rst)) {
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dev_err(&pdev->dev, "Can't get ehci reset\n");
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err = PTR_ERR(tegra->rst);
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goto cleanup_hcd_create;
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}
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err = clk_prepare_enable(tegra->clk);
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if (err)
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goto cleanup_hcd_create;
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err = tegra_reset_usb_controller(pdev);
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if (err)
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goto cleanup_clk_en;
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u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
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if (IS_ERR(u_phy)) {
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err = -EPROBE_DEFER;
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goto cleanup_clk_en;
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}
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hcd->usb_phy = u_phy;
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tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
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"nvidia,needs-double-reset");
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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hcd->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(hcd->regs)) {
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err = PTR_ERR(hcd->regs);
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goto cleanup_clk_en;
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}
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hcd->rsrc_start = res->start;
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hcd->rsrc_len = resource_size(res);
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ehci->caps = hcd->regs + 0x100;
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ehci->has_hostpc = soc_config->has_hostpc;
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err = usb_phy_init(hcd->usb_phy);
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|
if (err) {
|
|
dev_err(&pdev->dev, "Failed to initialize phy\n");
|
|
goto cleanup_clk_en;
|
|
}
|
|
|
|
u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
|
|
GFP_KERNEL);
|
|
if (!u_phy->otg) {
|
|
err = -ENOMEM;
|
|
goto cleanup_phy;
|
|
}
|
|
u_phy->otg->host = hcd_to_bus(hcd);
|
|
|
|
err = usb_phy_set_suspend(hcd->usb_phy, 0);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Failed to power on the phy\n");
|
|
goto cleanup_phy;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (!irq) {
|
|
dev_err(&pdev->dev, "Failed to get IRQ\n");
|
|
err = -ENODEV;
|
|
goto cleanup_phy;
|
|
}
|
|
|
|
otg_set_host(u_phy->otg, &hcd->self);
|
|
|
|
err = usb_add_hcd(hcd, irq, IRQF_SHARED);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Failed to add USB HCD\n");
|
|
goto cleanup_otg_set_host;
|
|
}
|
|
device_wakeup_enable(hcd->self.controller);
|
|
|
|
return err;
|
|
|
|
cleanup_otg_set_host:
|
|
otg_set_host(u_phy->otg, NULL);
|
|
cleanup_phy:
|
|
usb_phy_shutdown(hcd->usb_phy);
|
|
cleanup_clk_en:
|
|
clk_disable_unprepare(tegra->clk);
|
|
cleanup_hcd_create:
|
|
usb_put_hcd(hcd);
|
|
return err;
|
|
}
|
|
|
|
static int tegra_ehci_remove(struct platform_device *pdev)
|
|
{
|
|
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
|
struct tegra_ehci_hcd *tegra =
|
|
(struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
|
|
|
|
otg_set_host(hcd->usb_phy->otg, NULL);
|
|
|
|
usb_phy_shutdown(hcd->usb_phy);
|
|
usb_remove_hcd(hcd);
|
|
|
|
clk_disable_unprepare(tegra->clk);
|
|
|
|
usb_put_hcd(hcd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
|
|
|
if (hcd->driver->shutdown)
|
|
hcd->driver->shutdown(hcd);
|
|
}
|
|
|
|
static struct platform_driver tegra_ehci_driver = {
|
|
.probe = tegra_ehci_probe,
|
|
.remove = tegra_ehci_remove,
|
|
.shutdown = tegra_ehci_hcd_shutdown,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = tegra_ehci_of_match,
|
|
}
|
|
};
|
|
|
|
static int tegra_ehci_reset(struct usb_hcd *hcd)
|
|
{
|
|
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
|
int retval;
|
|
int txfifothresh;
|
|
|
|
retval = ehci_setup(hcd);
|
|
if (retval)
|
|
return retval;
|
|
|
|
/*
|
|
* We should really pull this value out of tegra_ehci_soc_config, but
|
|
* to avoid needing access to it, make use of the fact that Tegra20 is
|
|
* the only one so far that needs a value of 10, and Tegra20 is the
|
|
* only one which doesn't set has_hostpc.
|
|
*/
|
|
txfifothresh = ehci->has_hostpc ? 0x10 : 10;
|
|
ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct ehci_driver_overrides tegra_overrides __initconst = {
|
|
.extra_priv_size = sizeof(struct tegra_ehci_hcd),
|
|
.reset = tegra_ehci_reset,
|
|
};
|
|
|
|
static int __init ehci_tegra_init(void)
|
|
{
|
|
if (usb_disabled())
|
|
return -ENODEV;
|
|
|
|
pr_info(DRV_NAME ": " DRIVER_DESC "\n");
|
|
|
|
ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
|
|
|
|
/*
|
|
* The Tegra HW has some unusual quirks, which require Tegra-specific
|
|
* workarounds. We override certain hc_driver functions here to
|
|
* achieve that. We explicitly do not enhance ehci_driver_overrides to
|
|
* allow this more easily, since this is an unusual case, and we don't
|
|
* want to encourage others to override these functions by making it
|
|
* too easy.
|
|
*/
|
|
|
|
tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
|
|
tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
|
|
tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
|
|
|
|
return platform_driver_register(&tegra_ehci_driver);
|
|
}
|
|
module_init(ehci_tegra_init);
|
|
|
|
static void __exit ehci_tegra_cleanup(void)
|
|
{
|
|
platform_driver_unregister(&tegra_ehci_driver);
|
|
}
|
|
module_exit(ehci_tegra_cleanup);
|
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);
|