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![Lu Baolu](/assets/img/avatar_default.png)
xhci 1.1 capable controllers have a new HCCPARAMS2 registers with bits indicating support for new xhci 1.1 capabilities. Also add support for the new xhci 1.1 bits in the config operational opertational register that used to be reserved Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> [modified and left out parts not related to HCCPARAMS2 -Mathias] Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
614 lines
18 KiB
C
614 lines
18 KiB
C
/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "xhci.h"
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#define XHCI_INIT_VALUE 0x0
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/* Add verbose debugging later, just print everything for now */
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void xhci_dbg_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
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xhci->cap_regs);
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temp = readl(&xhci->cap_regs->hc_capbase);
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xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
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&xhci->cap_regs->hc_capbase, temp);
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xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n",
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(unsigned int) HC_LENGTH(temp));
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#if 0
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xhci_dbg(xhci, "// HCIVERSION: 0x%x\n",
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(unsigned int) HC_VERSION(temp));
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#endif
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xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
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temp = readl(&xhci->cap_regs->run_regs_off);
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xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
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&xhci->cap_regs->run_regs_off,
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(unsigned int) temp & RTSOFF_MASK);
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xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
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temp = readl(&xhci->cap_regs->db_off);
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xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
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xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
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}
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static void xhci_print_cap_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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u32 hci_version;
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xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
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temp = readl(&xhci->cap_regs->hc_capbase);
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hci_version = HC_VERSION(temp);
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xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
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(unsigned int) temp);
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xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
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(unsigned int) HC_LENGTH(temp));
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xhci_dbg(xhci, "HCIVERSION: 0x%x\n", hci_version);
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temp = readl(&xhci->cap_regs->hcs_params1);
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xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Max device slots: %u\n",
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(unsigned int) HCS_MAX_SLOTS(temp));
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xhci_dbg(xhci, " Max interrupters: %u\n",
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(unsigned int) HCS_MAX_INTRS(temp));
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xhci_dbg(xhci, " Max ports: %u\n",
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(unsigned int) HCS_MAX_PORTS(temp));
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temp = readl(&xhci->cap_regs->hcs_params2);
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xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Isoc scheduling threshold: %u\n",
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(unsigned int) HCS_IST(temp));
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xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n",
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(unsigned int) HCS_ERST_MAX(temp));
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temp = readl(&xhci->cap_regs->hcs_params3);
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xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n",
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(unsigned int) HCS_U1_LATENCY(temp));
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xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n",
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(unsigned int) HCS_U2_LATENCY(temp));
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temp = readl(&xhci->cap_regs->hcc_params);
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xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
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xhci_dbg(xhci, " HC generates %s bit addresses\n",
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HCC_64BIT_ADDR(temp) ? "64" : "32");
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xhci_dbg(xhci, " HC %s Contiguous Frame ID Capability\n",
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HCC_CFC(temp) ? "has" : "hasn't");
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xhci_dbg(xhci, " HC %s generate Stopped - Short Package event\n",
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HCC_SPC(temp) ? "can" : "can't");
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/* FIXME */
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xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n");
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temp = readl(&xhci->cap_regs->run_regs_off);
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xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
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/* xhci 1.1 controllers have the HCCPARAMS2 register */
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if (hci_version > 100) {
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temp = readl(&xhci->cap_regs->hcc_params2);
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xhci_dbg(xhci, "HCC PARAMS2 0x%x:\n", (unsigned int) temp);
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xhci_dbg(xhci, " HC %s Force save context capability",
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HCC2_FSC(temp) ? "supports" : "doesn't support");
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xhci_dbg(xhci, " HC %s Large ESIT Payload Capability",
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HCC2_LEC(temp) ? "supports" : "doesn't support");
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xhci_dbg(xhci, " HC %s Extended TBC capability",
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HCC2_ETC(temp) ? "supports" : "doesn't support");
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}
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}
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static void xhci_print_command_reg(struct xhci_hcd *xhci)
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{
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u32 temp;
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temp = readl(&xhci->op_regs->command);
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xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
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xhci_dbg(xhci, " HC is %s\n",
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(temp & CMD_RUN) ? "running" : "being stopped");
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xhci_dbg(xhci, " HC has %sfinished hard reset\n",
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(temp & CMD_RESET) ? "not " : "");
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xhci_dbg(xhci, " Event Interrupts %s\n",
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(temp & CMD_EIE) ? "enabled " : "disabled");
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xhci_dbg(xhci, " Host System Error Interrupts %s\n",
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(temp & CMD_HSEIE) ? "enabled " : "disabled");
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xhci_dbg(xhci, " HC has %sfinished light reset\n",
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(temp & CMD_LRESET) ? "not " : "");
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}
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static void xhci_print_status(struct xhci_hcd *xhci)
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{
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u32 temp;
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temp = readl(&xhci->op_regs->status);
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xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
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xhci_dbg(xhci, " Event ring is %sempty\n",
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(temp & STS_EINT) ? "not " : "");
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xhci_dbg(xhci, " %sHost System Error\n",
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(temp & STS_FATAL) ? "WARNING: " : "No ");
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xhci_dbg(xhci, " HC is %s\n",
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(temp & STS_HALT) ? "halted" : "running");
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}
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static void xhci_print_op_regs(struct xhci_hcd *xhci)
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{
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xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
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xhci_print_command_reg(xhci);
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xhci_print_status(xhci);
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}
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static void xhci_print_ports(struct xhci_hcd *xhci)
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{
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__le32 __iomem *addr;
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int i, j;
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int ports;
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char *names[NUM_PORT_REGS] = {
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"status",
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"power",
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"link",
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"reserved",
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};
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ports = HCS_MAX_PORTS(xhci->hcs_params1);
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addr = &xhci->op_regs->port_status_base;
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for (i = 0; i < ports; i++) {
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for (j = 0; j < NUM_PORT_REGS; ++j) {
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xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
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addr, names[j],
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(unsigned int) readl(addr));
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addr++;
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}
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}
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}
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void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
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{
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struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
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void __iomem *addr;
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u32 temp;
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u64 temp_64;
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addr = &ir_set->irq_pending;
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temp = readl(addr);
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if (temp == XHCI_INIT_VALUE)
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return;
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xhci_dbg(xhci, " %p: ir_set[%i]\n", ir_set, set_num);
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xhci_dbg(xhci, " %p: ir_set.pending = 0x%x\n", addr,
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(unsigned int)temp);
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addr = &ir_set->irq_control;
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temp = readl(addr);
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xhci_dbg(xhci, " %p: ir_set.control = 0x%x\n", addr,
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(unsigned int)temp);
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addr = &ir_set->erst_size;
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temp = readl(addr);
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xhci_dbg(xhci, " %p: ir_set.erst_size = 0x%x\n", addr,
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(unsigned int)temp);
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addr = &ir_set->rsvd;
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temp = readl(addr);
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if (temp != XHCI_INIT_VALUE)
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xhci_dbg(xhci, " WARN: %p: ir_set.rsvd = 0x%x\n",
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addr, (unsigned int)temp);
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addr = &ir_set->erst_base;
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temp_64 = xhci_read_64(xhci, addr);
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xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n",
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addr, temp_64);
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addr = &ir_set->erst_dequeue;
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temp_64 = xhci_read_64(xhci, addr);
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xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n",
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addr, temp_64);
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}
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void xhci_print_run_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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int i;
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xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
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temp = readl(&xhci->run_regs->microframe_index);
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xhci_dbg(xhci, " %p: Microframe index = 0x%x\n",
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&xhci->run_regs->microframe_index,
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(unsigned int) temp);
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for (i = 0; i < 7; ++i) {
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temp = readl(&xhci->run_regs->rsvd[i]);
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if (temp != XHCI_INIT_VALUE)
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xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n",
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&xhci->run_regs->rsvd[i],
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i, (unsigned int) temp);
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}
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}
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void xhci_print_registers(struct xhci_hcd *xhci)
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{
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xhci_print_cap_regs(xhci);
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xhci_print_op_regs(xhci);
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xhci_print_ports(xhci);
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}
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void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
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{
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int i;
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for (i = 0; i < 4; ++i)
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xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
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i*4, trb->generic.field[i]);
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}
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/**
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* Debug a transfer request block (TRB).
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*/
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void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
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{
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u64 address;
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u32 type = le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK;
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switch (type) {
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case TRB_TYPE(TRB_LINK):
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xhci_dbg(xhci, "Link TRB:\n");
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xhci_print_trb_offsets(xhci, trb);
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address = le64_to_cpu(trb->link.segment_ptr);
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xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
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xhci_dbg(xhci, "Interrupter target = 0x%x\n",
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GET_INTR_TARGET(le32_to_cpu(trb->link.intr_target)));
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xhci_dbg(xhci, "Cycle bit = %u\n",
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le32_to_cpu(trb->link.control) & TRB_CYCLE);
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xhci_dbg(xhci, "Toggle cycle bit = %u\n",
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le32_to_cpu(trb->link.control) & LINK_TOGGLE);
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xhci_dbg(xhci, "No Snoop bit = %u\n",
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le32_to_cpu(trb->link.control) & TRB_NO_SNOOP);
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break;
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case TRB_TYPE(TRB_TRANSFER):
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address = le64_to_cpu(trb->trans_event.buffer);
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/*
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* FIXME: look at flags to figure out if it's an address or if
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* the data is directly in the buffer field.
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*/
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xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
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break;
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case TRB_TYPE(TRB_COMPLETION):
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address = le64_to_cpu(trb->event_cmd.cmd_trb);
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xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
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xhci_dbg(xhci, "Completion status = %u\n",
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GET_COMP_CODE(le32_to_cpu(trb->event_cmd.status)));
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xhci_dbg(xhci, "Flags = 0x%x\n",
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le32_to_cpu(trb->event_cmd.flags));
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break;
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default:
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xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
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(unsigned int) type>>10);
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xhci_print_trb_offsets(xhci, trb);
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break;
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}
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}
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/**
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* Debug a segment with an xHCI ring.
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*
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* @return The Link TRB of the segment, or NULL if there is no Link TRB
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* (which is a bug, since all segments must have a Link TRB).
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*
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* Prints out all TRBs in the segment, even those after the Link TRB.
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*
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* XXX: should we print out TRBs that the HC owns? As long as we don't
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* write, that should be fine... We shouldn't expect that the memory pointed to
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* by the TRB is valid at all. Do we care about ones the HC owns? Probably,
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* for HC debugging.
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*/
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void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
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{
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int i;
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u64 addr = seg->dma;
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union xhci_trb *trb = seg->trbs;
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for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
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trb = &seg->trbs[i];
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xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", addr,
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lower_32_bits(le64_to_cpu(trb->link.segment_ptr)),
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upper_32_bits(le64_to_cpu(trb->link.segment_ptr)),
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le32_to_cpu(trb->link.intr_target),
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le32_to_cpu(trb->link.control));
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addr += sizeof(*trb);
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}
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}
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void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
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{
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xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",
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ring->dequeue,
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(unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg,
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ring->dequeue));
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xhci_dbg(xhci, "Ring deq updated %u times\n",
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ring->deq_updates);
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xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",
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ring->enqueue,
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(unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg,
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ring->enqueue));
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xhci_dbg(xhci, "Ring enq updated %u times\n",
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ring->enq_updates);
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}
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/**
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* Debugging for an xHCI ring, which is a queue broken into multiple segments.
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*
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* Print out each segment in the ring. Check that the DMA address in
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* each link segment actually matches the segment's stored DMA address.
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* Check that the link end bit is only set at the end of the ring.
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* Check that the dequeue and enqueue pointers point to real data in this ring
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* (not some other ring).
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*/
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void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
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{
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/* FIXME: Throw an error if any segment doesn't have a Link TRB */
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struct xhci_segment *seg;
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struct xhci_segment *first_seg = ring->first_seg;
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xhci_debug_segment(xhci, first_seg);
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if (!ring->enq_updates && !ring->deq_updates) {
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xhci_dbg(xhci, " Ring has not been updated\n");
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return;
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}
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for (seg = first_seg->next; seg != first_seg; seg = seg->next)
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xhci_debug_segment(xhci, seg);
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}
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void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
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unsigned int slot_id, unsigned int ep_index,
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struct xhci_virt_ep *ep)
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{
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int i;
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struct xhci_ring *ring;
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if (ep->ep_state & EP_HAS_STREAMS) {
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for (i = 1; i < ep->stream_info->num_streams; i++) {
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ring = ep->stream_info->stream_rings[i];
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xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n",
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slot_id, ep_index, i);
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xhci_debug_segment(xhci, ring->deq_seg);
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}
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} else {
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ring = ep->ring;
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if (!ring)
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return;
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|
xhci_dbg(xhci, "Dev %d endpoint ring %d:\n",
|
|
slot_id, ep_index);
|
|
xhci_debug_segment(xhci, ring->deq_seg);
|
|
}
|
|
}
|
|
|
|
void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
|
|
{
|
|
u64 addr = erst->erst_dma_addr;
|
|
int i;
|
|
struct xhci_erst_entry *entry;
|
|
|
|
for (i = 0; i < erst->num_entries; ++i) {
|
|
entry = &erst->entries[i];
|
|
xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n",
|
|
addr,
|
|
lower_32_bits(le64_to_cpu(entry->seg_addr)),
|
|
upper_32_bits(le64_to_cpu(entry->seg_addr)),
|
|
le32_to_cpu(entry->seg_size),
|
|
le32_to_cpu(entry->rsvd));
|
|
addr += sizeof(*entry);
|
|
}
|
|
}
|
|
|
|
void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
|
|
{
|
|
u64 val;
|
|
|
|
val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
|
|
xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
|
|
lower_32_bits(val));
|
|
xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
|
|
upper_32_bits(val));
|
|
}
|
|
|
|
/* Print the last 32 bytes for 64-byte contexts */
|
|
static void dbg_rsvd64(struct xhci_hcd *xhci, u64 *ctx, dma_addr_t dma)
|
|
{
|
|
int i;
|
|
for (i = 0; i < 4; ++i) {
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx "
|
|
"(dma) %#08llx - rsvd64[%d]\n",
|
|
&ctx[4 + i], (unsigned long long)dma,
|
|
ctx[4 + i], i);
|
|
dma += 8;
|
|
}
|
|
}
|
|
|
|
char *xhci_get_slot_state(struct xhci_hcd *xhci,
|
|
struct xhci_container_ctx *ctx)
|
|
{
|
|
struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
|
|
|
|
switch (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state))) {
|
|
case SLOT_STATE_ENABLED:
|
|
return "enabled/disabled";
|
|
case SLOT_STATE_DEFAULT:
|
|
return "default";
|
|
case SLOT_STATE_ADDRESSED:
|
|
return "addressed";
|
|
case SLOT_STATE_CONFIGURED:
|
|
return "configured";
|
|
default:
|
|
return "reserved";
|
|
}
|
|
}
|
|
|
|
static void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
|
|
{
|
|
/* Fields are 32 bits wide, DMA addresses are in bytes */
|
|
int field_size = 32 / 8;
|
|
int i;
|
|
|
|
struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
|
|
dma_addr_t dma = ctx->dma +
|
|
((unsigned long)slot_ctx - (unsigned long)ctx->bytes);
|
|
int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
|
|
|
|
xhci_dbg(xhci, "Slot Context:\n");
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
|
|
&slot_ctx->dev_info,
|
|
(unsigned long long)dma, slot_ctx->dev_info);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
|
|
&slot_ctx->dev_info2,
|
|
(unsigned long long)dma, slot_ctx->dev_info2);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
|
|
&slot_ctx->tt_info,
|
|
(unsigned long long)dma, slot_ctx->tt_info);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
|
|
&slot_ctx->dev_state,
|
|
(unsigned long long)dma, slot_ctx->dev_state);
|
|
dma += field_size;
|
|
for (i = 0; i < 4; ++i) {
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
|
|
&slot_ctx->reserved[i], (unsigned long long)dma,
|
|
slot_ctx->reserved[i], i);
|
|
dma += field_size;
|
|
}
|
|
|
|
if (csz)
|
|
dbg_rsvd64(xhci, (u64 *)slot_ctx, dma);
|
|
}
|
|
|
|
static void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
|
|
struct xhci_container_ctx *ctx,
|
|
unsigned int last_ep)
|
|
{
|
|
int i, j;
|
|
int last_ep_ctx = 31;
|
|
/* Fields are 32 bits wide, DMA addresses are in bytes */
|
|
int field_size = 32 / 8;
|
|
int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
|
|
|
|
if (last_ep < 31)
|
|
last_ep_ctx = last_ep + 1;
|
|
for (i = 0; i < last_ep_ctx; ++i) {
|
|
unsigned int epaddr = xhci_get_endpoint_address(i);
|
|
struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i);
|
|
dma_addr_t dma = ctx->dma +
|
|
((unsigned long)ep_ctx - (unsigned long)ctx->bytes);
|
|
|
|
xhci_dbg(xhci, "%s Endpoint %02d Context (ep_index %02d):\n",
|
|
usb_endpoint_out(epaddr) ? "OUT" : "IN",
|
|
epaddr & USB_ENDPOINT_NUMBER_MASK, i);
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
|
|
&ep_ctx->ep_info,
|
|
(unsigned long long)dma, ep_ctx->ep_info);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
|
|
&ep_ctx->ep_info2,
|
|
(unsigned long long)dma, ep_ctx->ep_info2);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",
|
|
&ep_ctx->deq,
|
|
(unsigned long long)dma, ep_ctx->deq);
|
|
dma += 2*field_size;
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
|
|
&ep_ctx->tx_info,
|
|
(unsigned long long)dma, ep_ctx->tx_info);
|
|
dma += field_size;
|
|
for (j = 0; j < 3; ++j) {
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
|
|
&ep_ctx->reserved[j],
|
|
(unsigned long long)dma,
|
|
ep_ctx->reserved[j], j);
|
|
dma += field_size;
|
|
}
|
|
|
|
if (csz)
|
|
dbg_rsvd64(xhci, (u64 *)ep_ctx, dma);
|
|
}
|
|
}
|
|
|
|
void xhci_dbg_ctx(struct xhci_hcd *xhci,
|
|
struct xhci_container_ctx *ctx,
|
|
unsigned int last_ep)
|
|
{
|
|
int i;
|
|
/* Fields are 32 bits wide, DMA addresses are in bytes */
|
|
int field_size = 32 / 8;
|
|
dma_addr_t dma = ctx->dma;
|
|
int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
|
|
|
|
if (ctx->type == XHCI_CTX_TYPE_INPUT) {
|
|
struct xhci_input_control_ctx *ctrl_ctx =
|
|
xhci_get_input_control_ctx(ctx);
|
|
if (!ctrl_ctx) {
|
|
xhci_warn(xhci, "Could not get input context, bad type.\n");
|
|
return;
|
|
}
|
|
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
|
|
&ctrl_ctx->drop_flags, (unsigned long long)dma,
|
|
ctrl_ctx->drop_flags);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
|
|
&ctrl_ctx->add_flags, (unsigned long long)dma,
|
|
ctrl_ctx->add_flags);
|
|
dma += field_size;
|
|
for (i = 0; i < 6; ++i) {
|
|
xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",
|
|
&ctrl_ctx->rsvd2[i], (unsigned long long)dma,
|
|
ctrl_ctx->rsvd2[i], i);
|
|
dma += field_size;
|
|
}
|
|
|
|
if (csz)
|
|
dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma);
|
|
}
|
|
|
|
xhci_dbg_slot_ctx(xhci, ctx);
|
|
xhci_dbg_ep_ctx(xhci, ctx, last_ep);
|
|
}
|
|
|
|
void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
|
|
const char *fmt, ...)
|
|
{
|
|
struct va_format vaf;
|
|
va_list args;
|
|
|
|
va_start(args, fmt);
|
|
vaf.fmt = fmt;
|
|
vaf.va = &args;
|
|
xhci_dbg(xhci, "%pV\n", &vaf);
|
|
trace(&vaf);
|
|
va_end(args);
|
|
}
|
|
EXPORT_SYMBOL_GPL(xhci_dbg_trace);
|