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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
66 lines
2.1 KiB
C
66 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* omap-dmic.h -- OMAP Digital Microphone Controller
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*/
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#ifndef _OMAP_DMIC_H
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#define _OMAP_DMIC_H
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#define OMAP_DMIC_REVISION_REG 0x00
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#define OMAP_DMIC_SYSCONFIG_REG 0x10
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#define OMAP_DMIC_IRQSTATUS_RAW_REG 0x24
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#define OMAP_DMIC_IRQSTATUS_REG 0x28
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#define OMAP_DMIC_IRQENABLE_SET_REG 0x2C
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#define OMAP_DMIC_IRQENABLE_CLR_REG 0x30
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#define OMAP_DMIC_IRQWAKE_EN_REG 0x34
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#define OMAP_DMIC_DMAENABLE_SET_REG 0x38
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#define OMAP_DMIC_DMAENABLE_CLR_REG 0x3C
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#define OMAP_DMIC_DMAWAKEEN_REG 0x40
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#define OMAP_DMIC_CTRL_REG 0x44
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#define OMAP_DMIC_DATA_REG 0x48
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#define OMAP_DMIC_FIFO_CTRL_REG 0x4C
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#define OMAP_DMIC_FIFO_DMIC1R_DATA_REG 0x50
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#define OMAP_DMIC_FIFO_DMIC1L_DATA_REG 0x54
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#define OMAP_DMIC_FIFO_DMIC2R_DATA_REG 0x58
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#define OMAP_DMIC_FIFO_DMIC2L_DATA_REG 0x5C
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#define OMAP_DMIC_FIFO_DMIC3R_DATA_REG 0x60
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#define OMAP_DMIC_FIFO_DMIC3L_DATA_REG 0x64
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/* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR bit fields */
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#define OMAP_DMIC_IRQ (1 << 0)
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#define OMAP_DMIC_IRQ_FULL (1 << 1)
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#define OMAP_DMIC_IRQ_ALMST_EMPTY (1 << 2)
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#define OMAP_DMIC_IRQ_EMPTY (1 << 3)
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#define OMAP_DMIC_IRQ_MASK 0x07
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/* DMIC_DMAENABLE bit fields */
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#define OMAP_DMIC_DMA_ENABLE 0x1
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/* DMIC_CTRL bit fields */
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#define OMAP_DMIC_UP1_ENABLE (1 << 0)
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#define OMAP_DMIC_UP2_ENABLE (1 << 1)
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#define OMAP_DMIC_UP3_ENABLE (1 << 2)
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#define OMAP_DMIC_UP_ENABLE_MASK 0x7
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#define OMAP_DMIC_FORMAT (1 << 3)
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#define OMAP_DMIC_POLAR1 (1 << 4)
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#define OMAP_DMIC_POLAR2 (1 << 5)
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#define OMAP_DMIC_POLAR3 (1 << 6)
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#define OMAP_DMIC_POLAR_MASK (0x7 << 4)
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#define OMAP_DMIC_CLK_DIV(x) (((x) & 0x7) << 7)
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#define OMAP_DMIC_CLK_DIV_MASK (0x7 << 7)
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#define OMAP_DMIC_RESET (1 << 10)
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#define OMAP_DMICOUTFORMAT_LJUST (0 << 3)
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#define OMAP_DMICOUTFORMAT_RJUST (1 << 3)
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/* DMIC_FIFO_CTRL bit fields */
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#define OMAP_DMIC_THRES_MAX 0xF
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enum omap_dmic_clk {
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OMAP_DMIC_SYSCLK_PAD_CLKS, /* PAD_CLKS */
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OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS, /* SLIMBUS_CLK */
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OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS, /* DMIC_SYNC_MUX_CLK */
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OMAP_DMIC_ABE_DMIC_CLK, /* abe_dmic_clk */
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};
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#endif
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