Conor Dooley efa310ba00 riscv: dts: microchip: hook up the mpfs' l2cache ... The initial PolarFire SoC devicetree must have been forked off from the fu540 one prior to the addition of l2cache controller support being added there. When the controller node was added to mpfs.dtsi, it was not hooked up to the CPUs & thus sysfs reports an incorrect cache configuration. Hook it up. Fixes: 0fa6107eca ("RISC-V: Initial DTS for Microchip ICICLE board") Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2022-07-05 16:54:03 +01:00
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dts	riscv: dts: microchip: hook up the mpfs' l2cache	2022-07-05 16:54:03 +01:00
.gitignore	RISC-V: ignore xipImage	2022-05-24 17:52:37 -07:00
install.sh	kbuild: factor out the common installation code into scripts/install.sh	2022-05-11 21:45:53 +09:00
loader.lds.S	riscv: Move kernel mapping outside of linear mapping	2021-04-26 08:25:04 -07:00
loader.S	riscv: provide a flat image loader	2019-11-17 15:17:39 -08:00
Makefile	riscv: move the (z)install rules to arch/riscv/Makefile	2021-09-10 23:08:26 -07:00