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![Mika Westerberg](/assets/img/avatar_default.png)
Some Alpine Ridge LP DROMs (there might be others) erroneusly list more ports than the controller actually has. Most probably because DROM of the full Dual/Single port Thunderbolt controller was reused for LP version. The current DROM parser does not check the upper bound thus it leads to crash when sw->ports[] is accessed over bounds: BUG: unable to handle kernel NULL pointer dereference at 00000000000002ec IP: tb_drom_read+0x383/0x890 [thunderbolt] PGD 0 P4D 0 Oops: 0000 [#1] SMP CPU: 3 PID: 12248 Comm: systemd-udevd Not tainted 4.13.0-rc1-next-20170719 #1 Hardware name: LENOVO 20HF000YGE/20HF000YGE, BIOS N1WET32W (1.11 ) 05/23/2017 task: ffff8a293e4bcd80 task.stack: ffffa698027a8000 RIP: 0010:tb_drom_read+0x383/0x890 [thunderbolt] RSP: 0018:ffffa698027ab990 EFLAGS: 00010246 RAX: 0000000000000000 RBX: ffff8a2940af7800 RCX: 0000000000000000 RDX: ffff8a2940ebb400 RSI: 0000000000000000 RDI: ffffa698027ab9a0 RBP: ffffa698027ab9d0 R08: 0000000000000001 R09: 0000000000000002 R10: ffff8a2940ebb5b0 R11: 0000000000000000 R12: ffff8a293bfa968c R13: 000000000000002c R14: 0000000000000056 R15: 0000000000000056 FS: 00007f0a945a38c0(0000) GS:ffff8a2961580000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00000000000002ec CR3: 000000043e785000 CR4: 00000000003606e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: tb_switch_add+0x9d/0x730 [thunderbolt] ? tb_switch_alloc+0x3cd/0x4d0 [thunderbolt] icm_start+0x5a/0xa0 [thunderbolt] tb_domain_add+0xc3/0xf0 [thunderbolt] nhi_probe+0x19e/0x310 [thunderbolt] local_pci_probe+0x42/0xa0 pci_device_probe+0x18d/0x1a0 driver_probe_device+0x2ff/0x450 __driver_attach+0xa4/0xe0 ? driver_probe_device+0x450/0x450 bus_for_each_dev+0x6e/0xb0 driver_attach+0x1e/0x20 bus_add_driver+0x1d0/0x270 ? 0xffffffffc0bbb000 driver_register+0x60/0xe0 ? 0xffffffffc0bbb000 __pci_register_driver+0x4c/0x50 nhi_init+0x28/0x1000 [thunderbolt] do_one_initcall+0x50/0x190 ? __vunmap+0x81/0xb0 ? _cond_resched+0x1a/0x50 ? kmem_cache_alloc_trace+0x15f/0x1c0 ? do_init_module+0x27/0x1e9 do_init_module+0x5f/0x1e9 load_module+0x24e7/0x2a60 ? vfs_read+0x115/0x130 SYSC_finit_module+0xfc/0x120 ? SYSC_finit_module+0xfc/0x120 SyS_finit_module+0xe/0x10 do_syscall_64+0x67/0x170 entry_SYSCALL64_slow_path+0x25/0x25 Fix this by making sure we only enumerate DROM port entries the hardware actually has. Reported-by: Christian Kellner <ckellner@redhat.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Lukas Wunner <lukas@wunner.de> Tested-by: Christian Kellner <ckellner@redhat.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
592 lines
13 KiB
C
592 lines
13 KiB
C
/*
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* Thunderbolt Cactus Ridge driver - eeprom access
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*
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* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
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*/
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#include <linux/crc32.h>
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#include <linux/property.h>
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#include <linux/slab.h>
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#include "tb.h"
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/**
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* tb_eeprom_ctl_write() - write control word
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*/
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static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
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{
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return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
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}
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/**
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* tb_eeprom_ctl_write() - read control word
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*/
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static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
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{
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return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
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}
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enum tb_eeprom_transfer {
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TB_EEPROM_IN,
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TB_EEPROM_OUT,
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};
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/**
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* tb_eeprom_active - enable rom access
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*
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* WARNING: Always disable access after usage. Otherwise the controller will
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* fail to reprobe.
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*/
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static int tb_eeprom_active(struct tb_switch *sw, bool enable)
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{
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struct tb_eeprom_ctl ctl;
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int res = tb_eeprom_ctl_read(sw, &ctl);
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if (res)
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return res;
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if (enable) {
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ctl.access_high = 1;
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res = tb_eeprom_ctl_write(sw, &ctl);
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if (res)
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return res;
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ctl.access_low = 0;
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return tb_eeprom_ctl_write(sw, &ctl);
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} else {
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ctl.access_low = 1;
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res = tb_eeprom_ctl_write(sw, &ctl);
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if (res)
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return res;
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ctl.access_high = 0;
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return tb_eeprom_ctl_write(sw, &ctl);
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}
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}
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/**
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* tb_eeprom_transfer - transfer one bit
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*
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* If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
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* If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
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*/
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static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
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enum tb_eeprom_transfer direction)
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{
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int res;
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if (direction == TB_EEPROM_OUT) {
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res = tb_eeprom_ctl_write(sw, ctl);
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if (res)
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return res;
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}
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ctl->clock = 1;
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res = tb_eeprom_ctl_write(sw, ctl);
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if (res)
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return res;
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if (direction == TB_EEPROM_IN) {
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res = tb_eeprom_ctl_read(sw, ctl);
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if (res)
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return res;
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}
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ctl->clock = 0;
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return tb_eeprom_ctl_write(sw, ctl);
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}
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/**
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* tb_eeprom_out - write one byte to the bus
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*/
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static int tb_eeprom_out(struct tb_switch *sw, u8 val)
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{
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struct tb_eeprom_ctl ctl;
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int i;
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int res = tb_eeprom_ctl_read(sw, &ctl);
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if (res)
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return res;
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for (i = 0; i < 8; i++) {
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ctl.data_out = val & 0x80;
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res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
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if (res)
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return res;
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val <<= 1;
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}
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return 0;
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}
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/**
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* tb_eeprom_in - read one byte from the bus
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*/
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static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
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{
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struct tb_eeprom_ctl ctl;
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int i;
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int res = tb_eeprom_ctl_read(sw, &ctl);
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if (res)
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return res;
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*val = 0;
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for (i = 0; i < 8; i++) {
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*val <<= 1;
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res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
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if (res)
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return res;
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*val |= ctl.data_in;
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}
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return 0;
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}
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/**
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* tb_eeprom_read_n - read count bytes from offset into val
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*/
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static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
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size_t count)
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{
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int i, res;
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res = tb_eeprom_active(sw, true);
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if (res)
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return res;
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res = tb_eeprom_out(sw, 3);
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if (res)
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return res;
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res = tb_eeprom_out(sw, offset >> 8);
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if (res)
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return res;
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res = tb_eeprom_out(sw, offset);
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if (res)
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return res;
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for (i = 0; i < count; i++) {
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res = tb_eeprom_in(sw, val + i);
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if (res)
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return res;
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}
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return tb_eeprom_active(sw, false);
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}
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static u8 tb_crc8(u8 *data, int len)
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{
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int i, j;
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u8 val = 0xff;
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for (i = 0; i < len; i++) {
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val ^= data[i];
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for (j = 0; j < 8; j++)
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val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
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}
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return val;
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}
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static u32 tb_crc32(void *data, size_t len)
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{
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return ~__crc32c_le(~0, data, len);
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}
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#define TB_DROM_DATA_START 13
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struct tb_drom_header {
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/* BYTE 0 */
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u8 uid_crc8; /* checksum for uid */
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/* BYTES 1-8 */
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u64 uid;
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/* BYTES 9-12 */
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u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
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/* BYTE 13 */
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u8 device_rom_revision; /* should be <= 1 */
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u16 data_len:10;
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u8 __unknown1:6;
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/* BYTES 16-21 */
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u16 vendor_id;
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u16 model_id;
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u8 model_rev;
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u8 eeprom_rev;
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} __packed;
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enum tb_drom_entry_type {
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/* force unsigned to prevent "one-bit signed bitfield" warning */
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TB_DROM_ENTRY_GENERIC = 0U,
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TB_DROM_ENTRY_PORT,
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};
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struct tb_drom_entry_header {
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u8 len;
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u8 index:6;
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bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
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enum tb_drom_entry_type type:1;
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} __packed;
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struct tb_drom_entry_generic {
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struct tb_drom_entry_header header;
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u8 data[0];
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} __packed;
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struct tb_drom_entry_port {
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/* BYTES 0-1 */
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struct tb_drom_entry_header header;
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/* BYTE 2 */
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u8 dual_link_port_rid:4;
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u8 link_nr:1;
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u8 unknown1:2;
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bool has_dual_link_port:1;
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/* BYTE 3 */
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u8 dual_link_port_nr:6;
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u8 unknown2:2;
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/* BYTES 4 - 5 TODO decode */
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u8 micro2:4;
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u8 micro1:4;
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u8 micro3;
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/* BYTES 6-7, TODO: verify (find hardware that has these set) */
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u8 peer_port_rid:4;
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u8 unknown3:3;
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bool has_peer_port:1;
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u8 peer_port_nr:6;
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u8 unknown4:2;
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} __packed;
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/**
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* tb_eeprom_get_drom_offset - get drom offset within eeprom
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*/
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static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
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{
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struct tb_cap_plug_events cap;
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int res;
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if (!sw->cap_plug_events) {
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tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
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return -ENOSYS;
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}
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res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
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sizeof(cap) / 4);
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if (res)
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return res;
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if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
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tb_sw_warn(sw, "no NVM\n");
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return -ENOSYS;
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}
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if (cap.drom_offset > 0xffff) {
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tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
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cap.drom_offset);
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return -ENXIO;
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}
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*offset = cap.drom_offset;
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return 0;
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}
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/**
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* tb_drom_read_uid_only - read uid directly from drom
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*
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* Does not use the cached copy in sw->drom. Used during resume to check switch
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* identity.
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*/
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int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
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{
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u8 data[9];
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u16 drom_offset;
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u8 crc;
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int res = tb_eeprom_get_drom_offset(sw, &drom_offset);
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if (res)
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return res;
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if (drom_offset == 0)
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return -ENODEV;
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/* read uid */
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res = tb_eeprom_read_n(sw, drom_offset, data, 9);
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if (res)
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return res;
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crc = tb_crc8(data + 1, 8);
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if (crc != data[0]) {
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tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n",
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data[0], crc);
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return -EIO;
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}
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*uid = *(u64 *)(data+1);
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return 0;
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}
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static int tb_drom_parse_entry_generic(struct tb_switch *sw,
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struct tb_drom_entry_header *header)
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{
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const struct tb_drom_entry_generic *entry =
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(const struct tb_drom_entry_generic *)header;
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switch (header->index) {
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case 1:
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/* Length includes 2 bytes header so remove it before copy */
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sw->vendor_name = kstrndup(entry->data,
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header->len - sizeof(*header), GFP_KERNEL);
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if (!sw->vendor_name)
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return -ENOMEM;
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break;
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case 2:
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sw->device_name = kstrndup(entry->data,
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header->len - sizeof(*header), GFP_KERNEL);
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if (!sw->device_name)
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return -ENOMEM;
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break;
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}
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return 0;
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}
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static int tb_drom_parse_entry_port(struct tb_switch *sw,
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struct tb_drom_entry_header *header)
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{
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struct tb_port *port;
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int res;
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enum tb_port_type type;
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/*
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* Some DROMs list more ports than the controller actually has
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* so we skip those but allow the parser to continue.
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*/
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if (header->index > sw->config.max_port_number) {
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dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n");
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return 0;
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}
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port = &sw->ports[header->index];
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port->disabled = header->port_disabled;
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if (port->disabled)
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return 0;
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res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
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if (res)
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return res;
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type &= 0xffffff;
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if (type == TB_TYPE_PORT) {
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struct tb_drom_entry_port *entry = (void *) header;
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if (header->len != sizeof(*entry)) {
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tb_sw_warn(sw,
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"port entry has size %#x (expected %#zx)\n",
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header->len, sizeof(struct tb_drom_entry_port));
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return -EIO;
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}
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port->link_nr = entry->link_nr;
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if (entry->has_dual_link_port)
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port->dual_link_port =
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&port->sw->ports[entry->dual_link_port_nr];
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}
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return 0;
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}
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/**
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* tb_drom_parse_entries - parse the linked list of drom entries
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*
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* Drom must have been copied to sw->drom.
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*/
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static int tb_drom_parse_entries(struct tb_switch *sw)
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{
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struct tb_drom_header *header = (void *) sw->drom;
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u16 pos = sizeof(*header);
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u16 drom_size = header->data_len + TB_DROM_DATA_START;
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int res;
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while (pos < drom_size) {
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struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
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if (pos + 1 == drom_size || pos + entry->len > drom_size
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|| !entry->len) {
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tb_sw_warn(sw, "drom buffer overrun, aborting\n");
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return -EIO;
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}
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switch (entry->type) {
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case TB_DROM_ENTRY_GENERIC:
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res = tb_drom_parse_entry_generic(sw, entry);
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break;
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case TB_DROM_ENTRY_PORT:
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res = tb_drom_parse_entry_port(sw, entry);
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break;
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}
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if (res)
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return res;
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pos += entry->len;
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}
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return 0;
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}
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/**
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* tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
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*/
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static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size)
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{
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struct device *dev = &sw->tb->nhi->pdev->dev;
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int len, res;
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len = device_property_read_u8_array(dev, "ThunderboltDROM", NULL, 0);
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if (len < 0 || len < sizeof(struct tb_drom_header))
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return -EINVAL;
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sw->drom = kmalloc(len, GFP_KERNEL);
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if (!sw->drom)
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return -ENOMEM;
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res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
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len);
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if (res)
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goto err;
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*size = ((struct tb_drom_header *)sw->drom)->data_len +
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TB_DROM_DATA_START;
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if (*size > len)
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goto err;
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return 0;
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err:
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kfree(sw->drom);
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sw->drom = NULL;
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return -EINVAL;
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}
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static int tb_drom_copy_nvm(struct tb_switch *sw, u16 *size)
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{
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u32 drom_offset;
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int ret;
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if (!sw->dma_port)
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return -ENODEV;
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ret = tb_sw_read(sw, &drom_offset, TB_CFG_SWITCH,
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sw->cap_plug_events + 12, 1);
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if (ret)
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return ret;
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if (!drom_offset)
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return -ENODEV;
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ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size,
|
|
sizeof(*size));
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Size includes CRC8 + UID + CRC32 */
|
|
*size += 1 + 8 + 4;
|
|
sw->drom = kzalloc(*size, GFP_KERNEL);
|
|
if (!sw->drom)
|
|
return -ENOMEM;
|
|
|
|
ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size);
|
|
if (ret)
|
|
goto err_free;
|
|
|
|
/*
|
|
* Read UID from the minimal DROM because the one in NVM is just
|
|
* a placeholder.
|
|
*/
|
|
tb_drom_read_uid_only(sw, &sw->uid);
|
|
return 0;
|
|
|
|
err_free:
|
|
kfree(sw->drom);
|
|
sw->drom = NULL;
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* tb_drom_read - copy drom to sw->drom and parse it
|
|
*/
|
|
int tb_drom_read(struct tb_switch *sw)
|
|
{
|
|
u16 drom_offset;
|
|
u16 size;
|
|
u32 crc;
|
|
struct tb_drom_header *header;
|
|
int res;
|
|
if (sw->drom)
|
|
return 0;
|
|
|
|
if (tb_route(sw) == 0) {
|
|
/*
|
|
* Apple's NHI EFI driver supplies a DROM for the root switch
|
|
* in a device property. Use it if available.
|
|
*/
|
|
if (tb_drom_copy_efi(sw, &size) == 0)
|
|
goto parse;
|
|
|
|
/* Non-Apple hardware has the DROM as part of NVM */
|
|
if (tb_drom_copy_nvm(sw, &size) == 0)
|
|
goto parse;
|
|
|
|
/*
|
|
* The root switch contains only a dummy drom (header only,
|
|
* no entries). Hardcode the configuration here.
|
|
*/
|
|
tb_drom_read_uid_only(sw, &sw->uid);
|
|
|
|
sw->ports[1].link_nr = 0;
|
|
sw->ports[2].link_nr = 1;
|
|
sw->ports[1].dual_link_port = &sw->ports[2];
|
|
sw->ports[2].dual_link_port = &sw->ports[1];
|
|
|
|
sw->ports[3].link_nr = 0;
|
|
sw->ports[4].link_nr = 1;
|
|
sw->ports[3].dual_link_port = &sw->ports[4];
|
|
sw->ports[4].dual_link_port = &sw->ports[3];
|
|
|
|
/* Port 5 is inaccessible on this gen 1 controller */
|
|
if (sw->config.device_id == PCI_DEVICE_ID_INTEL_LIGHT_RIDGE)
|
|
sw->ports[5].disabled = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
res = tb_eeprom_get_drom_offset(sw, &drom_offset);
|
|
if (res)
|
|
return res;
|
|
|
|
res = tb_eeprom_read_n(sw, drom_offset + 14, (u8 *) &size, 2);
|
|
if (res)
|
|
return res;
|
|
size &= 0x3ff;
|
|
size += TB_DROM_DATA_START;
|
|
tb_sw_info(sw, "reading drom (length: %#x)\n", size);
|
|
if (size < sizeof(*header)) {
|
|
tb_sw_warn(sw, "drom too small, aborting\n");
|
|
return -EIO;
|
|
}
|
|
|
|
sw->drom = kzalloc(size, GFP_KERNEL);
|
|
if (!sw->drom)
|
|
return -ENOMEM;
|
|
res = tb_eeprom_read_n(sw, drom_offset, sw->drom, size);
|
|
if (res)
|
|
goto err;
|
|
|
|
parse:
|
|
header = (void *) sw->drom;
|
|
|
|
if (header->data_len + TB_DROM_DATA_START != size) {
|
|
tb_sw_warn(sw, "drom size mismatch, aborting\n");
|
|
goto err;
|
|
}
|
|
|
|
crc = tb_crc8((u8 *) &header->uid, 8);
|
|
if (crc != header->uid_crc8) {
|
|
tb_sw_warn(sw,
|
|
"drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
|
|
header->uid_crc8, crc);
|
|
goto err;
|
|
}
|
|
if (!sw->uid)
|
|
sw->uid = header->uid;
|
|
sw->vendor = header->vendor_id;
|
|
sw->device = header->model_id;
|
|
|
|
crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
|
|
if (crc != header->data_crc32) {
|
|
tb_sw_warn(sw,
|
|
"drom data crc32 mismatch (expected: %#x, got: %#x), continuing\n",
|
|
header->data_crc32, crc);
|
|
}
|
|
|
|
if (header->device_rom_revision > 2)
|
|
tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
|
|
header->device_rom_revision);
|
|
|
|
return tb_drom_parse_entries(sw);
|
|
err:
|
|
kfree(sw->drom);
|
|
sw->drom = NULL;
|
|
return -EIO;
|
|
|
|
}
|