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c6a2d839d0
OMAP3 PM code for off-mode currently saves the scratchpad contents for CM registers within OMAP control module driver. However, as we are separating CM code into its own driver, this must be moved also. This patch adds a new API for saving the CM scratchpad contents and uses this from the high level scratchpad save function. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
92 lines
3 KiB
C
92 lines
3 KiB
C
/*
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* OMAP2/3 Clock Management (CM) register definitions
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*
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* Copyright (C) 2007-2009 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The CM hardware modules on the OMAP2/3 are quite similar to each
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* other. The CM modules/instances on OMAP4 are quite different, so
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* they are handled in a separate file.
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*/
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#ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H
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#define __ARCH_ASM_MACH_OMAP2_CM3XXX_H
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#include "prcm-common.h"
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#include "cm2xxx_3xxx.h"
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#define OMAP34XX_CM_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
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/*
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* OMAP3-specific global CM registers
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* Use cm_{read,write}_reg() with these registers.
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* These registers appear once per CM module.
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*/
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#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
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#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
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#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
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#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
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#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
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/*
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* Module specific CM register offsets from CM_BASE + domain offset
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* Use cm_{read,write}_mod_reg() with these registers.
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* These register offsets generally appear in more than one PRCM submodule.
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*/
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/* OMAP3-specific register offsets */
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#define OMAP3430_CM_CLKEN_PLL 0x0004
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#define OMAP3430ES2_CM_CLKEN2 0x0004
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#define OMAP3430ES2_CM_FCLKEN3 0x0008
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#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
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#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
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#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
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#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
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#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
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#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
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#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
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#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
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#define OMAP3430_CM_CLKSTST 0x004c
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#define OMAP3430ES2_CM_CLKSEL4 0x004c
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#define OMAP3430ES2_CM_CLKSEL5 0x0050
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#define OMAP3430_CM_CLKSEL2_EMU 0x0050
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#define OMAP3430_CM_CLKSEL3_EMU 0x0054
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/* CM_IDLEST bit field values to indicate deasserted IdleReq */
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#define OMAP34XX_CM_IDLEST_VAL 1
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#ifndef __ASSEMBLER__
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extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
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extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
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extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
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extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
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extern bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
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extern int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
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u8 idlest_shift);
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extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
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s16 *prcm_inst, u8 *idlest_reg_id);
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extern void omap3_cm_save_context(void);
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extern void omap3_cm_restore_context(void);
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extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
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extern int __init omap3xxx_cm_init(void);
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#endif
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#endif
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